Ethernet Design Example Components User Guide

Download PDF
ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

3.4.3. Control Signals

Table 34.  Control Signals Description
Name Direction Width Description
tx_etstamp_ins_ctrl_in_ingress_timestamp_96b In 96 The 96-bit ingress timestamp of the TX Packet, aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_in_ingress_timestamp_64b In 64 The 64-bit ingress timestamp of the TX Packet, aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_out_ingress_timestamp_96b Out 96 The 96-bit timestamp to the MAC TX, aligned to the corresponding output PTP packet.
tx_etstamp_ins_ctrl_out_ingress_timestamp_64b Out 64 The 64-bit timestamp to the MAC TX, aligned to the start of packet of the corresponding output PTP packet.
tx_egress_timestamp_request_in_valid In 1 Assert this signal to indicate that a timestamp is required for the packet. This signal must align to the start of an input packet.
tx_egress_timestamp_request_in_fingerprint In TSTAMP_FP_WIDTH The timestamp's fingerprint for the input packet.
tx_egress_timestamp_request_out_valid Out 1 Assert this signal when timestamp is required for the particular frame. This signal is aligned to the start of packet of the corresponding output PTP packet.
tx_egress_timestamp_request_out_fingerprint Out TSTAMP_FP_WIDTH The timestamp's fingerprint for the output packet.
clock mode In 2 Specify the clock mode:
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc In 1 Use this signal to indicate whether or not the incoming packet contains 4-byte CRC field.
  • 0: the incoming packet contains the CRC field.
  • 1: the incoming packet does not contain the CRC field.
tx_etstamp_ins_ctrl_in_residence_time_calc_format In 1 Use the following values to specify the format of the timestamp to use when calculating the residence time.
  • 0: 96-bit timestamp
  • 1: 64-bit timestamp
Align this signal to the start of the input packet.
tx_etstamp_ins_ctrl_out_residence_time_calc_format Out 1 The format of the timestamp used to calculate the residence time.
  • 0: 96-bit timestamp
  • 1: 64-bit timestamp
This signal is aligned to the start of the output packet.
tx_etstamp_ins_ctrl_out_checksum_zero Out 1 When asserted, indicates that the checksum field of the PTP packet is set to zero. This signal is aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_out_checksum_correct Out 1 When asserted, indicates that the checksum of the PTP packet is corrected by updating the checksum correction offset. This signal is aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_out_timestamp_format Out 1 The format of the timestamp.
  • 0: 1588v2 format. 96-bit timestamp that consists of 48-bit second field, 32-bit nanosecond field, and 16-bit correction field for fractional nanosecond.
  • 1: 1588v1 format. 64-bit timestamp that consists of 32-bit second field and 32-bit nanosecond field.
This signal is aligned to the start of packet of the corresponding output PTP packet.
tx_etstamp_ins_ctrl_out_timestamp_insert Out 1 When asserted, indicates that an egress timestamp must be inserted into the corresponding PTP packet. This signal is aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_out_residence_time_update Out 1 When asserted, indicates that the residence time is added to the correction field of the PTP packet. This signal is aligned to the start of packet of the corresponding PTP packet.
tx_etstamp_ins_ctrl_out_offset_timestamp Out 16 The location of the timestamp field, relative to the first byte of the packet.
tx_etstamp_ins_ctrl_out_offset_correction_field Out 16 The location of the correction field, relative to the first byte of the packet.
tx_etstamp_ins_ctrl_out_offset_checksum_field Out 16 The location of the checksum field, relative to the first byte of the packet.
tx_etstamp_ins_ctrl_out_offset_checksum_correction Out 16 The location of the checksum correction field, relative to the first byte of the packet.
Level Two Title