Ethernet Design Example Components User Guide

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ID 683044
Date 11/21/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.5.2. Time-of-day Signals

Table 11.  Time-of-day Signals Description
Name Direction Width Description
time_of_day_96[] Out 96 96-bit time of day streamed by the TOD clock.
time_of_day_64[] Out 64 64-bit time of day streamed by the TOD clock.
time_of_day_96b_load_valid In 1 Assert this signal for one clock cycle to indicate that the time_of_day_96b_load_data[] bus is valid. It indicates that the 96-bit time of day is synchronized and loaded into the TOD clock.
time_of_day_64b_load_valid In 1 Assert this signal for one clock cycle to indicate that the time_of_day_64b_load_data[] bus is valid. It indicates that the 64-bit time of day is synchronized and loaded into the TOD clock.
time_of_day_96b_load_data[] In 96 96-bit time of day from the master TOD clock.
time_of_day_64b_load_data[] In 64 64-bit time of day from the master TOD clock.
period_clk In 1 Clock for the TOD clock. Ensure that this clock is in the same clock domain as the TX and RX clock signals of the MAC IP.
period_rst_n In 1 Active-low reset signal for the period_clk domain. Synchronous to period_clk.
Level Two Title