Ethernet Design Example Components User Guide

Download PDF
ID 683044
Date 11/21/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.4.1. Adjusting TOD Drift

You can use the DriftAdjust and DriftAdjustRate registers to correct drifts in the TOD clock due to insufficient binary representation of the 16-bit fractional nanosecond field in the Period register.

For example, the Period register is set to 6.4 ns for a 10G Ethernet application. The hexadecimal representation of this value is 0x6 ns and 0x6666.4 fns.
  • Fractional nanosecond field is 16 bits wide: 0.4 fns = 0.4 * 216 = 26214.4 in decimal.
  • Converting to hexadecimal: 26214 + 0.4 = 0x6666 + 0x0000.4 = 0x6666.4 fns.
The fractional nanosecond value, 0x0000.4, cannot be represented in 16 bits thus causing the time of day to drift from the actual time by 0x0002 fns every 5 clock cycles. In other words, the time of day drifts 953.6 ns every 1 second. To correct this situation, configure the registers as follow:
  • DriftAdjust = 0x02, which sets the nanosecond field to 0x0 and the fractional nanosecond field to 0x2.
  • DriftAdjustRate = 0x5.
Level Two Title