Ethernet Design Example Components User Guide

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ID 683044
Date 11/21/2023
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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

3.4.2. Avalon® Streaming Interface Signals

Table 29.   Avalon® Streaming Signals Description
Name Direction Width Description
data_sink_sop In 1 Assert this signal to indicate the beginning of the packet.
data_sink_eop In 1 Assert this signal to indicate the end of the packet.
data_sink_valid In 1 Assert this signal to indicate that the data_sink_data[] signal and other signals on this interface are valid.
data_sink_ready Out 1 When asserted, this signal indicates that the packet classifier is ready to accept data.
data_sink_data[] In n 1 The input packet.
data_sink_empty[] In 2, 3 Use this signal to specify the number of empty bytes in the cycle that contain the end of packet.

The width of this signal is 2 when the SYMBOLSPERBEAT parameter is 4; 3 when the parameter is 8. This signal does not exist when the SYMBOLSPERBEAT is 1.

data_sink_error In 1 Assert this signal to indicate that the current input packet contains errors.
data_src_sop Out 1 When asserted, this signal indicates the beginning of the packet.
data_src_eop Out 1 When asserted, this signal indicates the end of the packet.
data_src_valid Out 1 When asserted, this signal indicates that the data_src_data[] signal and other signals on this interface are valid.
data_src_ready In 1 Assert this signal when the receiving component is ready to accept data.
data_src_data[] Out n 1 The output data.
data_src_empty[] Out 2, 3 Contains the number of empty bytes in the cycle that contain the end of packet.

The width of this signal is 2 when the SYMBOLSPERBEAT parameter is 4; 3 when the parameter is 8. This signal does not exist when the SYMBOLSPERBEAT is 1.

data_src_error Out 1 When asserted, this signal indicates that the current output packet contains errors.
1 n=SYMBOLSPERBEAT*BITSPERSYMBOL
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