Ethernet Design Example Components User Guide

Download PDF
ID 683044
Date 11/21/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface

To set up the IOPLL with dynamic phase shift interface and enable pulse per second (advanced accuracy mode) on a TOD Clock running on 125MHz period clock for Intel Agilex® 7 device, follow these steps:

  1. Create an Intel® Quartus® Prime project with Intel Agilex® 7 device selected.
  2. From IP Catalog, select IOPLL Intel FPGA IP.
  3. In IP Parameter Editor, apply the following settings and generate the IOPLL instance:
    1. Use the same clock source as TOD period_clk to drive IOPLL reference clock. Thus, set Reference Clock Frequency to 125 MHz.
    2. For Output Clocks section, set Number of Clocks to 2.
      1. Outclk0: Generate pps_sampling_clk, set Desired Frequency to 85.33MHz (pps_sampling_clk = period_clk *256/375). Sampling clock factor of 256/375 is suitable for all supported period_clk frequencies.
      2. Outclk1: Second clock port of the IOPLL must be allocated for TOD iopll_phased_clk. Set Desired Frequency to the same as TOD period_clk frequency (125MHz).
    3. In the same Output Clocks section, enable Specify VCO frequency and set Desired VCO Frequency to 1375 MHz.
      • Intel recommends you to specify the VCO frequency value as this value will be used to determine PLL unit phase shift parameter value of TOD. Otherwise, you can refer to Advanced Parameters tab for auto assigned VCO frequency.
    4. At Dynamic Reconfiguration tab, select Enable access to dynamic phase shift ports.
  4. From IP Catalog, select Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP.
  5. In IP Parameter Editor , apply the following settings and generate the TOD Clock instance:
    1. De-select Enable high clock frequency mode
    2. Set DEFAULT_NSEC_PERIOD to 8
    3. Set DEFAULT_FNSEC_PERIOD to 0x0
    4. Set DEFAULT_NSEC_ADJPERIOD to 8
    5. Set DEFAULT_FNSEC_ADJPERIOD to 0x0
    6. Select Enable pulse per second interface
    7. Select Advanced for Accuracy mode
    8. Enter desired value for Pulse width.
    9. Enter “100” for PLL scan clock frequency. This example uses 100 MHz as clock for iopll_scan_clk.
    10. Enter “90” for PLL unit phase shift. This example has set IOPLL VCO frequency to 1375 MHz, the unit phase shift equals to 1/8 of IOPLL VCO period, thus 90 ps.
    The diagram below illustrates the connection between IOPLL and TOD instances. Note that the diagram does not elaborate on all interfaces of the TOD instance.
    Figure 1.  Example of connections between IOPLL Interface and TOD Clock’s Advanced Accuracy Pulse Per Second Interface
Level Two Title