Ethernet Design Example Components User Guide

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ID 683044
Date 9/27/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.2. Resource Utilization

Table 3.  Estimated Resource Utilization in Stratix® V Devices
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K/MLAB)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

 727 733 1041 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

 1782 2406 2297 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

 764 736 1224 0
Table 4.  Estimated Resource Utilization in Intel® Arria® 10 Devices (10AX115U2F45I2SGES)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

 716 741 942 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

 1961 2735 2530 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

 689 734 1233 0
Table 5.  Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280LN2F43E1VG )
Configuration ALMs LUTs Logic Registers Memory

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 609 838 1312 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

ENABLE PPS = 0

 1633 2553 2401 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 897 896 2567 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 0

 628 879 1341 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 1

 1100 1729 1981 1
Table 6.  Estimated Resource Utilization in Intel® Agilex™ Devices (AGFA014F25AA212V)
Configuration ALMs LUT Logic Registers Memory

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 621 838 1312 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 1

ENABLE PPS = 0

 1629 2610 2532 0

PERIOD_CLOCK_FREQUENCY = 1

OFFSET_JITTER_WANDER_EN = 0

ENABLE PPS = 0

 894 912 2571 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 0

 602 819 1149 0

PERIOD_CLOCK_FREQUENCY = 0

OFFSET_JITTER_WANDER_EN = 0

ENABLE_PPS = 1

PPS_ADVANCE = 1

 1058 1689 1857 1
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