| 2021.09.27 |
21.3 |
19.3.0 |
- Added new section Pulse Per Second Device Speed Grade Support in the topic Release Information.
- Edited Resource Utilization and added Pulse Per Second Configuration to the following tables:
- Estimated Resource Utilization in Intel Arria 10 Devices (10AX115U2F45I2SGES).
- Estimated Resource Utilization in Intel Agilex Devices (AGFA014F25AA212V).
- Added new table: Pulse Per Second Parameter in Configuring the TOD Clock.
- Added new section IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) in Using the TOD Clock.
- Added new section Pulse-Per-Second Signals in the topic Interface Signals.
- Edited table: Register Description
- Changed Byte Offset to Word Offset.
- Added new row for 0x0B Word Offset.
- Removed Intel Max 10 as the Supported Devices from table: Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP Release Information.
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| 2021.03.29 |
21.1 |
19.2.0 |
- Added new tables:
- Sampling Clock Granularity for Sampling Clock Factor
- Sampling Clock Granularity Using 80 MHz Sampling Clock
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| 2020.12.14 |
20.4 |
19.2.0 |
- Updated chapter Time-of-day Synchronizer and table TOD Synchronizer Parameters Description to include frequency 402.83 MHz and also its parameters.
- Added figure TOD Synchronizer in a Design (SYNC_MODE 18) to section Using the TOD Synchronizer.
- Updated the description for clk_sampling in table Signals Description.
- Updated the names, values, default values, and descriptions for the following parameters in Table: TOD Clock Parameters Description:
- Updated parameter name PERIOD_CLOCK_FREQUENCY to Enable high clock frequency mode.
- Updated parameter name OFFSET_JITTER_WANDER_EN to Enable offset, jitter, and wander supports.
- Updated the description for AdjustPeriod in Table: Configuration Registers for Time-of-day clock.
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| 2020.07.14 |
20.2 |
19.2.0 |
Updated Adjusting Offset, Jitter, and Wander:
- Corrected the bits for WanderTimerLSB from [29:1] to [29:0].
- Corrected the values for WanderTimerMSB[15:0] from 0x06239 to 0x6239.
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| 2020.06.22 |
20.2 |
19.2.0 |
- Added the following tables in the Time-of-day Clock chapter:
- Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280LN2F43E1VG).
- Estimated Resource Utilization in Intel® Agilex™ Devices (AGFA014F25AA212V).
- Added the following tables in the Time-of-day Synchronizer chapter:
- Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SX280LN2F43E2LG)
- Estimated Resource Utilization in Intel® Agilex™ Devices (AGFB014F25A2E2V)
- Updated the description for PERIOD_CLOCK_FREQUENCY in Table: TOD Clock Parameters Description.
- Updated the following topics:
- Adjusting TOD Drift
- Adjusting Offset, Jitter, and Wander
- Correcting TOD Offset
- Packet Classifier
- Updated the description for the following registers in Table: Register Description:
- SecondsH
- AdjustPeriod
- AdjustCount
- Added a new Table: Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SX280LN2F43E2LG).
- Updated the descriptions to the following signals in Table: Control Signals Description:
- tx_etstamp_ins_ctrl_in_ingress_timestamp_96b
- tx_etstamp_ins_ctrl_in_ingress_timestamp_64b
- Updated for latest Intel® branding standards.
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| 2019.09.30 |
19.3 |
19.2.0 |
- Added support for Intel® Agilex™ devices in the Time-of-day Clock and Time-of-day Synchronizer chapters.
- Updated the following tables to include Intel® Quartus® Prime version:
- Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP Release Information
- Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP Release Information
- Ethernet Packet Classifier Intel® FPGA IP Release Information
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| 2019.07.01 |
19.2 |
19.2.0 |
- Renamed the Supported Devices sections to Release Information in the respective chapters to include IP release information as well as supported devices.
- Added support for Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices in the Time-of-day Clock and Time-of-day Synchronizer chapters.
- Added support for Intel® Stratix® 10 devices in the Packet Classifier chapter.
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| 2018.12.03 |
18.0 |
18.0 |
- Rebranded as Intel.
- Renamed the following Ethernet design example component names as per Intel rebranding:
- "Ethernet IEEE 1588 TOD Synchronizer" to "Ethernet IEEE 1588 TOD Synchronizer Intel FPGA IP"
- "Ethernet IEEE 1588 Time of Day Clock" to "Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP"
- "Ethernet Packet Classifier" to "Ethernet Packet Classifier Intel FPGA IP"
- Updated the following topics:
- Time-of-day Clock
- Using the TOD Clock
- Updated Table: Register Description to correct the byte offsets of SecondsL, NanoSec, Reserved, Period, AdjustPeriod, AdjustCount, DriftAdjust, DriftAdjustRate, OffsetNS, OffsetFNS, JitterTimer, JitterAdjust, WanderTimerLSB, and WanderAdjust registers.
- Made editorial updates throughout the document.
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