Intel® Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel® Quartus® Prime Programmer User Guide 3. Using the Intel® Quartus® Prime Programmer 4. Using the HPS Flash Programmer A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Intel® Quartus® Prime Pro Edition User Guides
2. Intel® Quartus® Prime Programmer User Guide x
2.1. Generating Primary Device Programming Files 2.2. Generating Secondary Programming Files 2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices 2.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 2.5. Generating Programming Files for Partial Reconfiguration 2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 2.7. Scripting Support 2.8. Generating Programming Files Revision History
2.2. Generating Secondary Programming Files x
2.2.1. Generating Secondary Programming Files (Programming File Generator) 2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 2.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
2.2.1. Generating Secondary Programming Files (Programming File Generator) x
2.2.1.1. Configuration Modes (Programming File Generator) 2.2.1.2. Secondary Programming Files (Programming File Generator)
2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
2.2.2.1. Secondary Programming Files (Convert Programming Files) 2.2.2.2. Configuration Modes (Convert Programming Files) 2.2.2.3. Debugging the Configuration (Convert Programming Files)
2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices x
2.3.1. Enabling Bitstream Authentication (Programming File Generator) 2.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 2.3.3. Enabling Bitstream Encryption (Programming File Generator)
2.5. Generating Programming Files for Partial Reconfiguration x
2.5.1. Generating PR Bitstream Files 2.5.2. Partial Reconfiguration Bitstream Compatibility Checking 2.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 2.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
2.6.1. Generating Programming Files for HPS Boot First Boot Flows 2.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
2.7. Scripting Support x
2.7.1. quartus_pfg Command Line Tool 2.7.2. quartus_cpf Command Line Tool
2.7.2. quartus_cpf Command Line Tool x
2.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
3. Using the Intel® Quartus® Prime Programmer x
3.1. Intel® Quartus® Prime Programmer 3.2. Programming and Configuration Modes 3.3. Basic Device Configuration Steps 3.4. Specifying the Programming Hardware Setup 3.5. Programming with Flash Loaders 3.6. Verifying the Programming File Source with Project Hash 3.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs) 3.8. Stand-Alone Programmer 3.9. Programmer Settings Reference 3.10. Scripting Support 3.11. Using the Intel® Quartus® Prime Programmer Revision History
3.4. Specifying the Programming Hardware Setup x
3.4.1. JTAG Chain Debugger Tool 3.4.2. Editing the Details of an Unknown Device 3.4.3. Running JTAG Daemon with Linux
3.4.1. JTAG Chain Debugger Tool x
3.4.1.1. JTAG Chain Integrity Tab 3.4.1.2. JTAG Chain Debugging Tab
3.5. Programming with Flash Loaders x
3.5.1. Specifying Flash Partitions 3.5.2. Full Erase of Flash Memory Sectors
3.6. Verifying the Programming File Source with Project Hash x
3.6.1. Obtaining Project Hash for Intel® Arria® 10 Devices
3.8. Stand-Alone Programmer x
3.8.1. Stand-Alone Programmer Memory Consumption
3.9. Programmer Settings Reference x
3.9.1. Device & Pin Options Dialog Box 3.9.2. More Security Options Dialog Box 3.9.3. Output Files Tab Settings (Programming File Generator) 3.9.4. Input Files Tab Settings (Programming File Generator) 3.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 3.9.6. Configuration Device Tab Settings 3.9.7. Add Partition Dialog Box (Programming File Generator) 3.9.8. Add Filesystem Dialog Box (Programming File Generator) 3.9.9. Convert Programming File Dialog Box 3.9.10. Compression and Encryption Settings (Convert Programming File) 3.9.11. SOF Data Properties Dialog Box (Convert Programming File) 3.9.12. Select Devices (Flash Loader) Dialog Box
3.10. Scripting Support x
3.10.1. The jtagconfig Debugging Tool
4. Using the HPS Flash Programmer x
4.1. HPS Flash Programmer Command-Line Utility 4.2. How the HPS Flash Programmer Works 4.3. Using the Flash Programmer from the Command Line 4.4. Supported Memory Devices 4.5. HPS Flash Programmer User Guide Revision History
4.3. Using the Flash Programmer from the Command Line x
4.3.1. HPS Flash Programmer 4.3.2. HPS Flash Programmer Command Line Examples
1. Answers to Top FAQs
2. Intel® Quartus® Prime Programmer User Guide
3. Using the Intel® Quartus® Prime Programmer
4. Using the HPS Flash Programmer
A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Intel® Quartus® Prime Pro Edition User Guides

2.2.2.3. Debugging the Configuration (Convert Programming Files)

Click the Advanced option in the Convert Programming Files dialog box to debug the file conversion configuration. Only choose advanced settings that apply to the design's target Intel FPGA device.

Changes in the Advanced Options dialog box affect .pof, .jic, .rpd, and .rbf file generation.

The following table describes the Advanced Options settings:

Table 6.  Advanced Options Settings
Option Setting Description Values
Disable EPCS/EPCQ ID check

Directs the FPGA to skips the EPCS/EPCQ silicon ID verification.

Applies to single and multi device AS configuration modes on all devices.

 Default setting is ON (EPCS/EPCQ ID check is enabled).
Disable AS mode CONF_DONE error check

Directs the FPGA to skip the CONF_DONE error check.

Applies to single- and multi-device (AS) configuration modes on all devices.

Default setting is OFF (AS mode CONF_DONE error check is enabled).

Program Length Count adjustment

Specifies the offset you can apply to the computed PLC of the entire bitstream.

Applies to single- and multi-device (AS) configuration modes on all FPGA devices.

Integer (Default = 0)
Post-chain bitstream pad bytes Specifies the number of pad bytes appended to the end of an entire bitstream.

If the bitstream of the last device is uncompressed, default value is 0.

Otherwise, default is 2
Post-device bitstream pad bytes

Specifies the number of pad bytes appended to the end of the bitstream of a device.

Applies to all single-device configuration modes on all FPGA devices.

Zero or positive integer.

Default is 0
Bitslice Padding Value

Specifies the padding value used to prepare bitslice configuration bitstreams, such that all bitslice configuration chains simultaneously receive their final configuration data bit.

Use only in 2, 4, and 8-bit PS configuration mode, when you use an EPC device with the decompression feature enabled.

Applies to all FPGA devices that support enhanced configuration devices.

0 or 1

Default value is 1

The following table lists possible symptoms of a failing configuration, and describes the advanced options necessary for configuration debugging.

Failure Symptoms Disable EPCS/EPCQ ID Check Disable AS Mode CONF_DONE Error Check PLC Settings Post-Chain Bitstream Pad Bytes Post-Device Bitstream Pad Bytes Bitslice Padding Value
Configuration failure occurs after a configuration cycle. — Yes Yes Yes 1 Yes 2 —
Decompression feature is enabled. — Yes Yes Yes 1 Yes 2 —
Encryption feature is enabled. — Yes Yes Yes 1 Yes 2 —
CONF_DONE stays low after a configuration cycle. — Yes Yes 3 Yes 1 Yes 2 —
CONF_DONE goes high momentarily after a configuration cycle. — Yes Yes 4 — — —
FPGA does not enter user mode even though CONF_DONE goes high. — — — Yes 1 Yes 2 —
Configuration failure occurs at the beginning of a configuration cycle. Yes — — — — —
EPCS128 Yes — — — — —
Failure in .pof generation for EPC device using Intel® Quartus® Prime Convert Programming File Utility when the decompression feature is enabled. — — — — — Yes
1 Use only for multi-device chain
2 Use only for single-device chain
3 Start with positive offset to the PLC settings
4 Start with negative offset to the PLC settings
Level Two Title