Intel® Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel® Quartus® Prime Programmer User Guide 3. Using the Intel® Quartus® Prime Programmer 4. Using the HPS Flash Programmer A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Intel® Quartus® Prime Pro Edition User Guides
2. Intel® Quartus® Prime Programmer User Guide x
2.1. Generating Primary Device Programming Files 2.2. Generating Secondary Programming Files 2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices 2.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 2.5. Generating Programming Files for Partial Reconfiguration 2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 2.7. Scripting Support 2.8. Generating Programming Files Revision History
2.2. Generating Secondary Programming Files x
2.2.1. Generating Secondary Programming Files (Programming File Generator) 2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 2.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
2.2.1. Generating Secondary Programming Files (Programming File Generator) x
2.2.1.1. Configuration Modes (Programming File Generator) 2.2.1.2. Secondary Programming Files (Programming File Generator)
2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
2.2.2.1. Secondary Programming Files (Convert Programming Files) 2.2.2.2. Configuration Modes (Convert Programming Files) 2.2.2.3. Debugging the Configuration (Convert Programming Files)
2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices x
2.3.1. Enabling Bitstream Authentication (Programming File Generator) 2.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 2.3.3. Enabling Bitstream Encryption (Programming File Generator)
2.5. Generating Programming Files for Partial Reconfiguration x
2.5.1. Generating PR Bitstream Files 2.5.2. Partial Reconfiguration Bitstream Compatibility Checking 2.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 2.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
2.6.1. Generating Programming Files for HPS Boot First Boot Flows 2.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
2.7. Scripting Support x
2.7.1. quartus_pfg Command Line Tool 2.7.2. quartus_cpf Command Line Tool
2.7.2. quartus_cpf Command Line Tool x
2.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
3. Using the Intel® Quartus® Prime Programmer x
3.1. Intel® Quartus® Prime Programmer 3.2. Programming and Configuration Modes 3.3. Basic Device Configuration Steps 3.4. Specifying the Programming Hardware Setup 3.5. Programming with Flash Loaders 3.6. Verifying the Programming File Source with Project Hash 3.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs) 3.8. Stand-Alone Programmer 3.9. Programmer Settings Reference 3.10. Scripting Support 3.11. Using the Intel® Quartus® Prime Programmer Revision History
3.4. Specifying the Programming Hardware Setup x
3.4.1. JTAG Chain Debugger Tool 3.4.2. Editing the Details of an Unknown Device 3.4.3. Running JTAG Daemon with Linux
3.4.1. JTAG Chain Debugger Tool x
3.4.1.1. JTAG Chain Integrity Tab 3.4.1.2. JTAG Chain Debugging Tab
3.5. Programming with Flash Loaders x
3.5.1. Specifying Flash Partitions 3.5.2. Full Erase of Flash Memory Sectors
3.6. Verifying the Programming File Source with Project Hash x
3.6.1. Obtaining Project Hash for Intel® Arria® 10 Devices
3.8. Stand-Alone Programmer x
3.8.1. Stand-Alone Programmer Memory Consumption
3.9. Programmer Settings Reference x
3.9.1. Device & Pin Options Dialog Box 3.9.2. More Security Options Dialog Box 3.9.3. Output Files Tab Settings (Programming File Generator) 3.9.4. Input Files Tab Settings (Programming File Generator) 3.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 3.9.6. Configuration Device Tab Settings 3.9.7. Add Partition Dialog Box (Programming File Generator) 3.9.8. Add Filesystem Dialog Box (Programming File Generator) 3.9.9. Convert Programming File Dialog Box 3.9.10. Compression and Encryption Settings (Convert Programming File) 3.9.11. SOF Data Properties Dialog Box (Convert Programming File) 3.9.12. Select Devices (Flash Loader) Dialog Box
3.10. Scripting Support x
3.10.1. The jtagconfig Debugging Tool
4. Using the HPS Flash Programmer x
4.1. HPS Flash Programmer Command-Line Utility 4.2. How the HPS Flash Programmer Works 4.3. Using the Flash Programmer from the Command Line 4.4. Supported Memory Devices 4.5. HPS Flash Programmer User Guide Revision History
4.3. Using the Flash Programmer from the Command Line x
4.3.1. HPS Flash Programmer 4.3.2. HPS Flash Programmer Command Line Examples
1. Answers to Top FAQs
2. Intel® Quartus® Prime Programmer User Guide
3. Using the Intel® Quartus® Prime Programmer
4. Using the HPS Flash Programmer
A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Intel® Quartus® Prime Pro Edition User Guides

2.2.2.2. Configuration Modes (Convert Programming Files)

Select one of the following Configuration modes in Convert Programming Files for generation of secondary programming files:
Table 5.  Convert Programming Files Configuration Modes
Programming Mode Description
1-Bit/2-Bit/4-Bit/8-Bit Passive Serial An external controller passes configuration data to one or more FPGA devices via a serial data stream. The FPGA device is a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU, or the Intel® Quartus® Prime Programmer, or an EPC2 or EPC16 configuration device.
Active Parallel Supports configuration devices using commodity 16-bit parallel flash memories to control the configuration interface.
Active Serial For storing configuration data in a low-cost serial configuration device with non-volatile memory. Serial configuration devices provide a serial interface to access the configuration data. During device configuration, the device reads the configuration data through the serial interface, decompresses the data if necessary, and configures their SRAM cells.
Active Serial x4
AVST x8/x16/x32 The Avalon® streaming configuration mode uses an external host, such as a microprocessor or Intel® MAX® 10 device. The external host controls the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host. You can use the PFL II IP core with an Intel® MAX® 10 device as the host to read configuration data from a flash memory device that configures an FPGA.
Passive Parallel Synchronous An external controller, such as a CPU, loads the design data into a device via a common data bus. Data is latched by the device on the first rising edge of a CPU-driven clock signal. The next eight falling clock edges serialize this latched data within the device. The device latches the next 8-bit byte of data on every eighth rising edge of the clock signal until the device is completely configured.
Passive Parallel Asynchronous An external controller, such as a CPU, loads the design data into a device via a common data bus. The device accepts a parallel byte of input data. Intelligent communication between the external controller and the device allows the external controller to configure the device.
Internal Configuration Uses a .pof file for internal configuration of the Intel® MAX® 10 device’s Configuration Flash Memory (CFM) and User Flash Memory (UFM) via a download cable Intel® Quartus® Prime Programmer.
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