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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Add Filesystem Dialog Box (Programming File Generator)
2.9.9. Convert Programming File Dialog Box
2.9.10. Compression and Encryption Settings (Convert Programming File)
2.9.11. SOF Data Properties Dialog Box (Convert Programming File)
2.9.12. Select Devices (Flash Loader) Dialog Box
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1.2.1.1. Configuration Modes (Programming File Generator)
Select one of the following Configuration modes in Programming File Generator for generation of secondary programming files:
Programming Mode | Description | Supports Devices |
---|---|---|
Active Serial x4 | For storing configuration data in a low-cost serial configuration device with non-volatile memory and four-pin interface. Serial configuration devices provide a serial interface to access the configuration data. During device configuration, Intel® Stratix® 10 devices read the configuration data through the serial interface, decompress the data if necessary, and configure their SRAM cells. |
|
AVST x8 | The Avalon® streaming configuration mode uses an external host, such as a microprocessor or Intel® MAX® 10 device. The external host controls the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host. You can use the PFL II IP core with an Intel® MAX® 10 device as the host to read configuration data from a flash memory device that configures an Intel® Stratix® 10 FPGA. | |
AVST x16 | ||
AVST x32 | ||
1-Bit Passive Serial | An external controller passes configuration data to one or more FPGA devices via a serial data stream. The FPGA device is a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU. | Intel® Cyclone® 10 LP |
Active Serial | Stores configuration data in a low-cost serial configuration device with non-volatile memory and four-pin interface. | |
Internal Configuration | Uses a .pof file for internal configuration of the Intel® MAX® 10 device’s Configuration Flash Memory (CFM) and User Flash Memory (UFM) via a download cable Intel® Quartus® Prime Programmer. | Intel® MAX® 10 |