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1. Intel Agilex® 7 Variable Precision DSP Blocks Overview
2. Intel Agilex® 7 Variable Precision DSP Blocks Architecture
3. Intel Agilex® 7 Variable Precision DSP Blocks Operational Modes
4. Intel Agilex® 7 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Intel Agilex® FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE Intel® FPGA IP Core References
10. Native Floating Point DSP Intel Agilex® FPGA IP References
11. Intel Agilex® 7 Variable Precision DSP Blocks User Guide Archives
12. Document Revision History for the Intel Agilex® 7 Variable Precision DSP Blocks User Guide
2.1.1. Input Register Bank for Fixed-point Arithmetic
2.1.2. Pipeline Registers for Fixed-point Arithmetic
2.1.3. Pre-adder for Fixed-point Arithmetic
2.1.4. Internal Coefficient for Fixed-point Arithmetic
2.1.5. Multipliers for Fixed-point Arithmetic
2.1.6. Adder or Subtractor for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
2.1.8. Systolic Register for Fixed-point Arithmetic
2.1.9. Double Accumulation Register for Fixed-point Arithmetic
2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2.1. Input Register Bank for Floating-point Arithmetic
2.2.2. Pipeline Registers for Floating-point Arithmetic
2.2.3. Multipliers for Floating-point Arithmetic
2.2.4. Adder or Subtractor for Floating-point Arithmetic
2.2.5. Output Register Bank for Floating-point Arithmetic
2.2.6. Exception Handling for Floating-point Arithmetic
3.2.2.1. FP16 Supported Precision Formats
3.2.2.2. Sum of Two FP16 Multiplication Mode
3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode
3.2.2.5. FP16 Vector One Mode
3.2.2.6. FP16 Vector Two Mode
3.2.2.7. FP16 Vector Three Mode
5.1. Native Fixed Point DSP Intel Agilex® FPGA IP Release Information
5.2. Supported Operational Modes
5.3. Maximum Input Data Width for Fixed-point Arithmetic
5.4. Maximum Output Data Width for Fixed-point Arithmetic
5.5. Parameterizing Native Fixed Point DSP IP
5.6. Native Fixed Point DSP Intel Agilex® FPGA IP Signals
5.7. IP Migration
10.1. Native Floating Point DSP Intel Agilex® FPGA IP Release Information
10.2. Native Floating Point DSP Intel Agilex® FPGA IP Core Supported Operational Modes
10.3. Parameterizing the Native Floating Point DSP Intel Agilex® FPGA IP
10.4. Native Floating Point DSP Intel Agilex® FPGA IP Core Signals
10.5. IP Migration
10.4.1. FP32 Multiplication Mode Signals
10.4.2. FP32 Addition or Subtraction Mode Signals
10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals
10.4.4. FP32 Multiplication with Accumulation Mode Signals
10.4.5. FP32 Vector One and Vector Two Modes Signals
10.4.6. Sum of Two FP16 Multiplication Mode Signals
10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals
10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals
10.4.9. FP16 Vector One and Vector Two Modes Signals
10.4.10. FP16 Vector Three Mode Signals
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1.1. Features
The Intel Agilex® 7 fixed-point arithmetic features include:
- High-performance, power-optimized, and fully registered multiplication operations
- 9-bit, 18-bit, and 27-bit word lengths
- Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
- Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
- Cascading 19-bit or 27-bit and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
- Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
- Hard pre-adder supported in 18-bit and 27-bit DSP operation modes for symmetric filters
- Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
- 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
- Biased rounding support
- Dynamically enable and disable scanin and chainout features
The Intel Agilex® 7 floating-point arithmetic is a completely hardened architecture. Features for floating-point arithmetic include :
- Single-precision (32-bit arithmetic) and half-precision (16-bit arithmetic) modes
- Operational mode for flushed, extended, and bfloat16 (Brain Floating Point) floating-point format
- Multiplication, addition, subtraction, multiply-add, and multiply-subtract
- Multiplication with accumulation capability and a dynamic accumulator reset control
- Multiplication with cascade summation and subtraction capability
- Complex multiplication
- Direct vector dot product
- Systolic vector dot product
- Sequential vector dot product
- Exception handling support using exception flags:-
- 8-bit exception flags for 32-bit arithmetic
- 16-bit exception flags for 16-bit arithmetic
- Subnormal values handling