Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Public
Document Table of Contents

5.5.6. Pipelining

Table 51.  Pipelining Tab
Parameter IP Generated Parameter Value Default Value Description
Input Pipeline Register
Enable input pipeline register to the input data signal (x/y/z/coefsel) input_pipeline_clken

no_reg

ena0

ena1

ena2

ena0

Specify the first pipeline register clock enable signal for x, y, z, and coefsel ports.

Select no_reg to disable the register.

Enable 2nd input pipeline register to the input data signal (x/y/z/coefsel) second_pipeline_clken

no_reg

ena0

ena1

ena2

ena0

Specify the second pipeline register clock enable signal for x, y, z, and coefsel ports.

Select no_reg to disable the register.

Accumulator Pipeline Register
Enable 'accumulate' input pipeline register accum_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the first pipeline register clock enable signal for accumulate port.

Select no_reg to disable the register.

Enable 'accumulate' 2nd input pipeline register accum_2nd_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the first pipeline register clock enable signal for accumulate port.

Select no_reg to disable the register.

Loadconst Pipeline Registers
Enable 'loadconst' input pipeline register load_const_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the first pipeline register clock enable signal for loadconst port.

Select no_reg to disable the register.

Enable 'loadconst' 2nd input pipeline register load_const_2nd_pipeline_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the second pipeline register clock enable signal for loadconst port.

Select no_reg to disable the register.

Systolic Configuration
Enable input systolic register input_systolic_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for the input systolic register.

Select no_reg to disable the register.