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1. Intel Agilex® 7 Variable Precision DSP Blocks Overview
2. Intel Agilex® 7 Variable Precision DSP Blocks Architecture
3. Intel Agilex® 7 Variable Precision DSP Blocks Operational Modes
4. Intel Agilex® 7 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Intel Agilex® FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE Intel® FPGA IP Core References
10. Native Floating Point DSP Intel Agilex® FPGA IP References
11. Intel Agilex® 7 Variable Precision DSP Blocks User Guide Archives
12. Document Revision History for the Intel Agilex® 7 Variable Precision DSP Blocks User Guide
2.1.1. Input Register Bank for Fixed-point Arithmetic
2.1.2. Pipeline Registers for Fixed-point Arithmetic
2.1.3. Pre-adder for Fixed-point Arithmetic
2.1.4. Internal Coefficient for Fixed-point Arithmetic
2.1.5. Multipliers for Fixed-point Arithmetic
2.1.6. Adder or Subtractor for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
2.1.8. Systolic Register for Fixed-point Arithmetic
2.1.9. Double Accumulation Register for Fixed-point Arithmetic
2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2.1. Input Register Bank for Floating-point Arithmetic
2.2.2. Pipeline Registers for Floating-point Arithmetic
2.2.3. Multipliers for Floating-point Arithmetic
2.2.4. Adder or Subtractor for Floating-point Arithmetic
2.2.5. Output Register Bank for Floating-point Arithmetic
2.2.6. Exception Handling for Floating-point Arithmetic
3.2.2.1. FP16 Supported Precision Formats
3.2.2.2. Sum of Two FP16 Multiplication Mode
3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode
3.2.2.5. FP16 Vector One Mode
3.2.2.6. FP16 Vector Two Mode
3.2.2.7. FP16 Vector Three Mode
5.1. Native Fixed Point DSP Intel Agilex® FPGA IP Release Information
5.2. Supported Operational Modes
5.3. Maximum Input Data Width for Fixed-point Arithmetic
5.4. Maximum Output Data Width for Fixed-point Arithmetic
5.5. Parameterizing Native Fixed Point DSP IP
5.6. Native Fixed Point DSP Intel Agilex® FPGA IP Signals
5.7. IP Migration
10.1. Native Floating Point DSP Intel Agilex® FPGA IP Release Information
10.2. Native Floating Point DSP Intel Agilex® FPGA IP Core Supported Operational Modes
10.3. Parameterizing the Native Floating Point DSP Intel Agilex® FPGA IP
10.4. Native Floating Point DSP Intel Agilex® FPGA IP Core Signals
10.5. IP Migration
10.4.1. FP32 Multiplication Mode Signals
10.4.2. FP32 Addition or Subtraction Mode Signals
10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals
10.4.4. FP32 Multiplication with Accumulation Mode Signals
10.4.5. FP32 Vector One and Vector Two Modes Signals
10.4.6. Sum of Two FP16 Multiplication Mode Signals
10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals
10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals
10.4.9. FP16 Vector One and Vector Two Modes Signals
10.4.10. FP16 Vector Three Mode Signals
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6.4. Signals
The following tables list the input and output signals of the Multiply Adder Intel® FPGA IP core.
Signal | Required | Description |
---|---|---|
dataa_0[]/dataa_1[]/dataa_2[]/dataa_3[] | Yes | Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 … 0] wide |
datab_0[]/datab_1[]/datab_2[]/datab_3[] | Yes | Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 … 0] wide |
datac_0[] /datac_1[]/datac_2[]/datac_3[] | No | Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C - 1, … 0] wide Select INPUT for Select preadder mode parameter to enable these signals. |
clock[1:0] | No | Clock input port to the corresponding register. This signal can be used by any register in the IP core. |
aclr[1:0] | No | Asynchronous clear input to the corresponding register. |
sclr[1:0] | No | Synchronous clear input to the corresponding register. |
ena[1:0] | No | Enable signal input to the corresponding register. |
signa | No | Specifies the numerical representation of the multiplier input A. If the signa signal is high, the multiplier treats the multiplier input A signal as a signed number. If the signa signal is low, the multiplier treats the multiplier input A signal as an unsigned number. Select VARIABLE for What is the representation format for Multipliers A inputs parameter to enable this signal. |
signb | No | Specifies the numerical representation of the multiplier input B signal. If the signb signal is high, the multiplier treats the multiplier input B signal as a signed two's complement number. If the signb signal is low, the multiplier treats the multiplier input B signal as an unsigned number. |
scanina[] | No | Input for scan chain A. Input signal [WIDTH_A - 1, ... 0] wide. When the INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is required. |
accum_sload | No | Dynamically specifies whether the accumulator value is constant. If the accum_sload signal is low, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously. |
sload_accum | No | Dynamically specifies whether the accumulator value is constant. If the sload_accum signal is high, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously. |
chainin[] | No | Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ - 1, … 0] wide. |
addnsub1 | No | Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the first pair of multipliers. |
addnsub3 | No | Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub3 signal to add the outputs from the second pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from the first pair of multipliers. |
coefsel0[] | No | Coefficient input signal[0:3] to the first multiplier. |
coefsel1[] | No | Coefficient input signal[0:3]to the second multiplier. |
coefsel2[] | No | Coefficient input signal[0:3]to the third multiplier. |
coefsel3[] | No | Coefficient input signal [0:3] to the fourth multiplier. |
Signal | Required | Description |
---|---|---|
result [] | Yes | Multiplier output signal. Output signal [WIDTH_RESULT - 1 … 0] wide |
scanouta [] | No | Output of scan chain A. Output signal [WIDTH_A - 1..0] wide. Select more than 2 for numbers of multipliers and choose Scan chain input for What is the input A of the multiplier connected to parameter to enable this signal. |