Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023
Public

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7.8. TOD Interface Signals

Table 26.  TOD Interface Signal
Signal Direction Width Description
master_pulse_per_second Out 1 Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms.
start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the TOD synchronization process. The time-of-day of the local TOD is synchronized to the time-of-day of the master TOD. The synchronization process continues as long as this signal remains asserted.
pulse_per_second_10g[] pulse_per_second Out [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms.
pulse_per_second_1g[] Out [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms.