Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 12/14/2023
Public

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7.4. PHY Interface Signals

Table 22.  PHY Interface Signals
Signal Direction Width Description
rx_serial_data In 2 RX serial input data
tx_serial_data Out 2 TX serial output data