Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

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ID 683025
Date 7/19/2019
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Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

3. Customizing the HLS AFU

You can substitute a different HLS component into the AFU in the HLS AFU design example to customize the accelerator.

To integrate an HLS component into an AFU, the AFU must provide the interfaces that your HLS component needs. You might need to update your host code as well.

At a high-level, to create an AFU from an HLS component, you must generate RTL for your component with the i++ command and then create a new UUID for the new AFU.

For details about how to create a UUID, see the Accelerator Functional Unit (AFU) Developer's Guide.

The steps that follow provide an example of how to replace the HLS component in the design example by replacing the fpVectorReduce_float component with the fpVectorReduce_ac_int component.

To replace the HLS component in the design example:

  1. Navigate to the qsys folder and create a new folder there called quartus_temp.
  2. Open the system with Platform Designer (from Intel® Quartus® Prime Pro Edition Version 17.1.1, provided with the Acceleration Stack) by running the following command from the qsys folder: 
    $ qsys-edit --search-path=../hls/test-fpga.prj/components/fpVectorReduce_float,\
../hls/test-fpga.prj/components/fpVectorReduce_ac_int,$ hls_afu_container.qsys
  3. To edit hls_afu_container.qsys, create an Intel® Quartus® Prime project by clicking Create New Quartus Project.
    Figure 5. New Quartus Project
  4. Create a quartus_temp_prj project in the quartus_temp folder.
  5. Click Open on the Open System window.
    Figure 6. Open System
  6. Optional: If you have a custom HLS component that has a new UUID for your component, enter the UUID it in the afu_id_avmm_slave component parameters.
    Enter the UUID as follows:
    1. In the AFU_ID_H field, enter the upper 64 bits of the UUID.
    2. In the AFU_ID_L field, enter the lower 64 bits of the UUID.
    The host program must also be updated with the new UUID information. For details, see Host Application Description.
    Figure 7. UUID
  7. Remove the fpVectorReduce_float component by right-clicking it and clicking Remove.
    Figure 8. Remove Component
  8. In the Delete IP Variant dialog box, click No so that Platform Designer does not delete the fpVectorReduce_float IP file.
  9. Search for the fpVectorReduce_ac_int component in IP Catalog. Double-click the component to add it to the system.
    Figure 9. Add Component
  10. In the Component Instantiation window, convert the absolute path for the IP file information to a relative path.
    To convert the path to a relative path, edit the location of the IP file information to delete all the text preceding the hls folder (including the leading "/" character) and replace it with ".." (two periods).

    Having a relative path here gives the .qsys file a relative path to your .ip file, so you can move your AFU project safely to a different file system.

    Figure 10. Absolute Path Before Deleting Text
    Figure 11. Relative Path After Deleting Text
  11. Connect the new HLS component. In this case, the new component is the fpVectorReduce_ac_int component.
    Make sure that you set the base address of your component Avalon-MM slave to 0x0040, so that the HLS component and AFU ID slave can share the same memory space, and the host application can access both.
    Figure 12. Set Base Address
  12. Click Validate System Integrity to update the Platform Designer system. A message appears at the bottom of the Platform Designer window indicating success.
  13. Save the system and exit Platform Designer.

    Click Yes if you are asked to generate the changes.

  14. Configure your AFU by modifying the Acceleration Stack configuration files hls_afu/filelist.txt and hls_afu/hls_afu.json.
    For examples of these files, see Acceleration Stack Configuration Files.
  15. Modify the host application to include the Avalon-MM slave register map that is produced by HLS.
    1. Copy the hls_afu/hw/rtl/hls/test-fpga.prj/components/fpVectorReduce_ac_int/fpVectorReduce_ac_int_csr.h header file to the host application project in hls_afu/sw/src.
    2. In hls_afu_host.c, include fpVectorReduce_ac_int_csr.h instead of fpVectorReduce_float_csr.h. Also replace the references to fpVectorReduce_float registers with references to fpVectorReduce_ac_int registers.

After you have customized the HLS AFU:

  1. Generate the ASE testbench.
  2. Compile the AF bitstream.
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