F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 7/08/2024
Public
Document Table of Contents

5.1. Clock Connections in Single Instance Operation

This clock connection describes a single IP core instantiation in your design.

This is a typical clock connection requirement in a single IP core.

You must make the following clock connections:
  • The i_clk_ref and the i_clk_sys clocks drive the IP core.
  • The output clock o_clk_pll drives both the i_clk_rx and the i_clk_tx input signals.
Figure 21. Typical Clock ConnectionsThis diagram displays single Ethernet IP core and its related clock signals.
Table 27.  Port Connection Guidelines between F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP and F-Tile Ethernet Intel® FPGA Hard IP
F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP F-Tile Ethernet Intel® FPGA Hard IP
System PLL
out_systempll_clk i_clk_sys
FGT
out_refclk_fgt i_clk_ref
FHT
out_fht_cmmpll_clk i_clk_ref