IEEE 1588 V2 Test: Intel FPGA Programmable Acceleration Card N3000

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ID 683017
Date 5/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. IXIA Traffic Test 3. lperf3 Traffic Test 4. Conclusion 5. Document Revision History for IEEE 1588 V2 Test
1. Introduction x
1.1. Background 1.2. Objective 1.3. Features and Limitations 1.4. Tools and Driver Versions
2. IXIA Traffic Test x
2.1. IXIA Traffic Test Result
3. lperf3 Traffic Test x
3.1. lperf3 Traffic Test Result
1. Introduction
2. IXIA Traffic Test
3. lperf3 Traffic Test
4. Conclusion
5. Document Revision History for IEEE 1588 V2 Test

1.2. Objective

These tests validate the use of Intel® FPGA PAC N3000 as the IEEE1588v2 slave in Open Radio Access Network (O-RAN). This document describes:
  • Test setup
  • Verification process
  • Performance evaluation of transparent clock mechanism in the FPGA path of Intel® FPGA PAC N3000
  • PTP performance of the Intel® FPGA PAC N3000

The performance of the Intel® FPGA PAC N3000 supporting the transparent clock is compared with the Intel® FPGA PAC N3000 without transparent clock as well as with another Ethernet card XXV710 under various traffic conditions and PTP configurations.

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