The FPGA data path between QSFP28 (25G MAC) and Intel XL710 (40G MAC) adds a variable packet latency which affects the approximation accuracy of the PTP Slave. Adding the Transparent Clock (T-TC) support in the FPGA soft logic of Intel® FPGA PAC N3000 provides compensation of this packet latency by appending its residence time in the correction field of encapsulated PTP messages. The results confirm that the T-TC mechanism improves the accuracy performance of the PTP4l slave.

Also, the IXIA Traffic Test Result show that the T-TC support in the FPGA data path enhances the PTP performance by at least 4x, when compared to the Intel® FPGA PAC N3000 without T-TC support. The Intel® FPGA PAC N3000 with T-TC presents a worst-case master offset of 53 ns under ingress, egress or bidirectional traffic loads at the limit of channel capacity (25 Gbps). Hence, with T-TC support, the Intel® FPGA PAC N3000 PTP performance is both more accurate and less prone to noise variations.

In lperf3 Traffic Test, the PTP performance of the Intel® FPGA PAC N3000 with T-TC enabled is compared against a XXV710 card. This test captured the PTP4l data for both slave clocks under ingress or egress traffic that is exchanged between the two hosts of Intel® FPGA PAC N3000 and XXV710 card. The worst-case master offset observed in the Intel® FPGA PAC N3000 is at least 5x lower than the XXV710 card. Also, the standard deviation of the captured offsets also proves that the T-TC support of Intel® FPGA PAC N3000 allows smoother approximation of the Grandmaster’s clock.