Serial Digital Interface (SDI) II Intel® FPGA IP Release Notes

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Date 7/08/2024
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1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes x
1.1. SDI II Intel® FPGA IP v19.5.0 1.2. SDI II Intel® FPGA IP v19.4.0 1.3. SDI II Intel® FPGA IP v19.3.2 1.4. SDI II Intel® FPGA IP v19.3.0 1.5. SDI II Intel® FPGA IP v19.2.1 1.6. SDI II Intel® FPGA IP v19.2 1.7. SDI II Intel® FPGA IP v19.1 1.8. SDI II Intel® FPGA IP v18.1 Update 2 1.9. SDI II Intel® FPGA IP v18.1 Update 1 1.10. SDI II Intel® FPGA IP v18.1 1.11. SDI II Intel® FPGA IP v18.0 1.12. Intel FPGA SDI II IP Core v17.1 1.13. SDI II IP Core v17.0 1.14. SDI II IP Core v16.1 1.15. SDI II IP Core v16.0 1.16. SDI II IP Core v15.1 1.17. SDI II IP Core v15.0 1.18. SDI II IP Core v14.1 1.19. Serial Digital Interface (SDI) II User Guide Archives
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes

1.16. SDI II IP Core v15.1

Table 17.  v15.1 November 2015
Description Impact
Redefined the rx_format signal. Each stream of 6G-SDI and 12G-SDI interfaces reports its own detected rx format. For example, when receiving 2160p60 in 12G-SDI, all 4 streams are expected to report 1080p60. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added new interface signals for Arria V, Cyclone V, and Stratix V devices:
  • rx_trs_in
  • pll_powerdown_in
  • pll_ powerdown_out
Added new reconfiguration management parameters for Arria 10 devices:
  • VIDEO_STANDARD
  • ED_TXPLL_SWITCH
  • XCVR_RCFG_IF_TYPE
Fixed jitter tolerance reduction issue when receiving SD-SDI video standards.
Updated the sdc constraint for the dual-clock FIFO (DCFIFO) component instantiated in the core.
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