Renamed the following as per Intel rebranding:
- SDI II IP core to Intel FPGA SDI II IP core
- Qsys to Platform Designer
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Added preliminary support for Stratix® 10 (H-Tile) devices. |
The Stratix® 10 devices are only available in the Quartus® Prime Pro Edition software. |
Added new design examples for Stratix® 10 devices. Refer to the Intel FPGA SDI II Design Example User Guide for Stratix® 10 Devices for more information. |
In previous versions of the Intel FPGA SDI II design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Quartus® Prime software version 17.1. |
If you are upgrading designs that have these additional constraints from the previous versions of the Quartus® Prime software to version 17.1, you must revise the constraints. Refer to the KDB page for more information. |