Renamed Intel FPGA SDI II IP to SDI II Intel® FPGA IP as part of standardizing and rebranding exercise. |
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Added support for Xcelium* Parallel simulator. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added a new parameter, Rx core clock (rx_coreclk) frequency. This parameter is available only when you select Multi rate (up to 12G) and Receiver or Bidirectional direction in the Quartus® Prime Pro Edition software. |
Updated the rx_coreclk_is_ntsc_paln signal to include 297.0 MHz and 296.70 MHz options. |
Added Parallel loopback without external VCXO option for Stratix® 10 design example. |
Added the following files:
- pid_controller.v
- rcfg_pll_frac.v
- modelsim_files.tcl
- ncsim_files.tcl
- riviera_files.tcl
- vcs_files.tcl
- vcsmx_files.tcl
- xcelium_files.tcl
- tb_ln_check.v
- cds.lib
- hdl.var
- xcelium_setup.sh
- xcelium_sim.sh
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Added final support for Cyclone® 10 GX devices. |
The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software. |
Added new design examples for Cyclone® 10 GX devices in version 17.1.1 release. Refer to the SDI II Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information. |