AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

Download PDF
ID 683012
Date 12/31/2019
Public
Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.2. Triple Rate SDI II VCXO Removal Reference Design

This reference design consists of channel 0—SDI II IP in transmitter and receiver IP cores in simplex mode.
Figure 8. Triple Rate SDI II VCXO Removal Reference Design Block DiagramThis figure shows a high-level block diagram of the triple rate SDI II VCXO removal reference design.

For more information about each component in the block diagram, refer to Reference Design Components.

Level Two Title