AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

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ID 683012
Date 12/31/2019
Public
Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.5. Document Revision History

Document Version Changes
2019.12.31 Added a note that recalibration is required after performing PLL reconfiguration in the SDI Reclock section.
2017.05.08 Rebranded as Intel.
2016.06.01
  • Removed the existing Triple Rate SDI II with External VCXO reference design version 15.0.
  • Added new reference designs for Quartus Prime version 16.0:
    • Triple Rate SDI II with External VCXO reference design
    • Triple Rate SDI II VCXO Removal reference design
  • Updated the PFD codes for external VCXO design.
  • Update the switch settings.
2015.08.31 Updated the document structure.
2015.06.29 Initial release.
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