AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

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ID 683012
Date 12/31/2019
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Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.2.2.1. Receiver

To run the test, connect an SDI signal generator to the receiver input, SDI_RX_P (J20), of channel 0.

This test uses the following user LEDs to indicate the respective conditions:
  • D8, D9 and D10 indicate the receiver signal standard.
  • D7 illuminates when the align_locked signal for channel 0 is asserted.
  • D6 illuminates when the trs_locked signal for channel 0 is asserted.
  • D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 11. User LEDs
Level Two Title