Visible to Intel only — GUID: GUID-FA527539-702B-4CF7-A17B-3A4B765C009D
Alphabetical Option List
General Rules for Compiler Options
What Appears in the Compiler Option Descriptions
Optimization Options
Code Generation Options
Interprocedural Optimization Options
Advanced Optimization Options
Profile Guided Optimization Options
Optimization Report Options
Offload Compilation, OpenMP*, and Parallel Processing Options
Floating-Point Options
Inlining Options
Output, Debug, and Precompiled Header Options
Preprocessor Options
Component Control Options
Language Options
Data Options
Compiler Diagnostic Options
Compatibility Options
Linking or Linker Options
Miscellaneous Options
Deprecated and Removed Compiler Options
Display Option Information
Alternate Compiler Options
Portability and GCC-Compatible Warning Options
arch
ax, Qax
EH
fasynchronous-unwind-tables
fcf-protection, Qcf-protection
fdata-sections, Gw
fexceptions
ffunction-sections, Gy
fomit-frame-pointer
Gd
GR
guard
Gv
m, Qm
m64, Qm64
m80387
march
masm
mauto-arch, Qauto-arch
mbranches-within-32B-boundaries, Qbranches-within-32B-boundaries
mintrinsic-promote, Qintrinsic-promote
momit-leaf-frame-pointer
mtune, tune
regcall, Qregcall
x, Qx
xHost, QxHost
ffreestanding, Qfreestanding
fjump-tables
fvec-peel-loops, Qvec-peel-loops
fvec-remainder-loops, Qvec-remainder-loops
fvec-with-mask, Qvec-with-mask
ipp-link, Qipp-link
mno-gather, Qgather-
mno-scatter, Qscatter-
qactypes, Qactypes
qdaal, Qdaal
qipp, Qipp
qmkl, Qmkl
qmkl-ilp64, Qmkl-ilp64
qopt-assume-no-loop-carried-dep, Qopt-assume-no-loop-carried-dep
qopt-dynamic-align, Qopt-dynamic-align
qopt-for-throughput, Qopt-for-throughput
qopt-mem-layout-trans, Qopt-mem-layout-trans
qopt-multiple-gather-scatter-by-shuffles, Qopt-multiple-gather-scatter-by-shuffles
qopt-prefetch, Qopt-prefetch
qopt-streaming-stores, Qopt-streaming-stores
qtbb, Qtbb
unroll, Qunroll
use-intel-optimized-headers, Quse-intel-optimized-headers
vec, Qvec
vec-threshold, Qvec-threshold
device-math-lib
fintelfpga
fiopenmp, Qiopenmp
flink-huge-device-code
fno-sycl-libspirv
foffload-static-lib
fopenmp
fopenmp-declare-target-scalar-defaultmap, Qopenmp-declare-target-scalar-defaultmap
fopenmp-device-lib
fopenmp-target-buffers, Qopenmp-target-buffers
fopenmp-targets, Qopenmp-targets
fsycl
fsycl-add-targets
fsycl-dead-args-optimization
fsycl-device-code-split
fsycl-device-lib
fsycl-device-obj
fsycl-device-only
fsycl-early-optimizations
fsycl-enable-function-pointers
fsycl-esimd-force-stateless-mem
fsycl-explicit-simd
fsycl-force-target
fsycl-help
fsycl-host-compiler
fsycl-host-compiler-options
fsycl-id-queries-fit-in-int
fsycl-instrument-device-code
fsycl-link
fsycl-link-huge-device-code
fsycl-link-targets
fsycl-max-parallel-link-jobs
fsycl-optimize-non-user-code
fsycl-rdc
fsycl-targets
fsycl-unnamed-lambda
fsycl-use-bitcode
ftarget-compile-fast
nolibsycl
qopenmp, Qopenmp
qopenmp-link
qopenmp-simd, Qopenmp-simd
qopenmp-stubs, Qopenmp-stubs
reuse-exe
Wno-sycl-strict
Xopenmp-target
Xs
Xsycl-target
ffp-contract
fimf-absolute-error, Qimf-absolute-error
fimf-accuracy-bits, Qimf-accuracy-bits
fimf-arch-consistency, Qimf-arch-consistency
fimf-domain-exclusion, Qimf-domain-exclusion
fimf-max-error, Qimf-max-error
fimf-precision, Qimf-precision
fimf-use-svml, Qimf-use-svml
fma, Qfma
fp-model, fp
fp-speculation, Qfp-speculation
ftz, Qftz
pc, Qpc
w
w, W
Wabi
Wall
Wcheck-unicode-security
Wcomment
Wdeprecated
Weffc++, Qeffc++
Werror, WX
Werror-all
Wextra-tokens
Wformat
Wformat-security
Wmain
Wmissing-declarations
Wmissing-prototypes
Wpointer-arith
Wreorder
Wreturn-type
Wshadow
Wsign-compare
Wstrict-aliasing
Wstrict-prototypes
Wtrigraphs
Wuninitialized
Wunknown-pragmas
Wunused-function
Wunused-variable
Wwrite-strings
Create Libraries
Use Intel Shared Libraries on Linux
Manage Libraries
Redistribute Libraries When Deploying Applications
Resolve References to Shared Libraries
Intel's Memory Allocator Library
SIMD Data Layout Templates
Intel® C++ Class Libraries
Intel's C++ Asynchronous I/O Extensions for Windows
IEEE 754-2008 Binary Floating-Point Conformance Library
Intel's Numeric String Conversion Library
Terms and Syntax
Rules for Operators
Assignment Operator
Logical Operators
Addition and Subtraction Operators
Multiplication Operators
Shift Operators
Comparison Operators
Conditional Select Operators
Debug Operations
Unpack Operators
Pack Operators
Clear MMX™ State Operator
Integer Functions for Intel® Streaming SIMD Extensions
Conversions between Fvec and Ivec
Fvec Syntax and Notation
Data Alignment
Conversions
Constructors and Initialization
Arithmetic Operators
Minimum and Maximum Operators
Logical Operators
Compare Operators
Conditional Select Operators for Fvec Classes
Cacheability Support Operators
Debug Operations
Load and Store Operators
Unpack Operators
Move Mask Operators
aio_read
aio_write
Example for aio_read and aio_write Functions
aio_suspend
Example for aio_suspend Function
aio_error
aio_return
Example for aio_error and aio_return Functions
aio_fsync
aio_cancel
Example for aio_cancel Function
lio_listio
Example for lio_listio Function
Asynchronous I/O Function Errors
Intel® IEEE 754-2008 Binary Floating-Point Conformance Library and Usage
Function List
Homogeneous General-Computational Operations Functions
General-Computational Operation Functions
Quiet-Computational Operations Functions
Signaling-Computational Operations Functions
Non-Computational Operations Functions
Compilation Overview
Supported Environment Variables
Pass Options to the Linker
Specify Alternate Tools and Paths
Use Configuration Files
Use Response Files
Global Symbols and Visibility Attributes for Linux*
Save Compiler Information in Your Executable
Link Debug Information
Ahead of Time Compilation
Device Offload Compilation Considerations
Use a Third-Party Compiler as a Host Compiler for SYCL Code
Visible to Intel only — GUID: GUID-FA527539-702B-4CF7-A17B-3A4B765C009D
Code Generation Options
This section contains descriptions for compiler options that pertain to code generation. They are listed in alphabetical order.
Parent topic: Compiler Options
- arch
Tells the compiler which features it may target, including which instruction sets it may generate. - ax, Qax
Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit. - EH
Specifies the model of exception handling to be performed. - fasynchronous-unwind-tables
Determines whether unwind information is precise at an instruction boundary or at a call boundary. - fcf-protection, Qcf-protection
Enables Intel® Control-Flow Enforcement Technology (Intel® CET) protection, which defends your program from certain attacks that exploit vulnerabilities. This option offers preliminary support for Intel® CET. - fdata-sections, Gw
Places each data item in its own COMDAT section. - fexceptions
Enables exception handling table generation. - ffunction-sections, Gy
Places each function in its own COMDAT section. - fomit-frame-pointer
Determines whether EBP is used as a general-purpose register in optimizations. - Gd
Makes __cdecl the default calling convention. - GR
Enables or disables C++ Runtime Type Information (RTTI). - guard
Enables control flow protection mechanisms. - Gv
Tells the compiler to use the vector calling convention (__vectorcall) when passing vector type arguments. - m, Qm
Tells the compiler which instruction set extensions based on CPUID bits it may generate. - m64, Qm64
Tells the compiler to generate code for a specific architecture. - m80387
Specifies whether the compiler can use x87 instructions. - march
Tells the compiler to generate code using the CPU feature set of a specific processor as the baseline. - masm
Tells the compiler to generate the assembler output file using a selected dialect. - mauto-arch, Qauto-arch
Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for x86 architecture processors if there is a performance benefit. - mbranches-within-32B-boundaries, Qbranches-within-32B-boundaries
Tells the compiler to align branches and fused branches on 32-byte boundaries for better performance. - mintrinsic-promote, Qintrinsic-promote
Enables functions containing calls to intrinsics that require a specific CPU feature to have their target architecture automatically promoted to allow the required feature. - momit-leaf-frame-pointer
Determines whether the frame pointer is omitted or kept in leaf functions. - mtune, tune
Performs optimizations for specific processors but does not cause extended instruction sets to be used (unlike -march). - regcall, Qregcall
Tells the compiler that the __regcall calling convention should be used for functions that do not directly specify a calling convention. - x, Qx
Tells the compiler which processor features it may target, including which instruction sets and optimizations it may generate. - xHost, QxHost
Tells the compiler to generate instructions for the highest instruction set available on the compilation host processor.