Archived External Memory IP Specifications
This page contains a list of archived external memory interface IP core specifications for previous version of Quartus® Prime Software.
Table 1. Archived External Memory IP Specifications
The specifications can be downloaded from the download link provided in the table.
| Description | Devices | Quartus® Software Version | Download |
|---|---|---|---|
| Quartus® Prime Software v24.2 specifications |
All | 24.2 | Download spreadsheet |
| Quartus® Prime Software v22.3 specifications | All | 22.3 | Download spreadsheet |
| Quartus® Prime Software v21.4 specifications | All | 21.4 | Download spreadsheet |
| Quartus® Prime Software v21.3 specifications | All | 21.3 | Download spreadsheet |
| Quartus® Prime Software v21.2 specifications | All | 21.2 | Download spreadsheet |
| Quartus® Prime Software v21.1 specifications | All | 21.1 | Download spreadsheet |
| Quartus® Prime Software v16.2 - v21.0 specifications1 | All | 16.2 - 21.01 | Not available (see notes for more information) |
Quartus® Prime software v16.1 specifications |
All |
16.1 |
|
Quartus® Prime software v16.0 specifications |
All |
16.0 |
|
Quartus® Prime software v15.1 specifications |
All |
15.1 |
|
Quartus® II software v15.0 specifications |
All |
15.0 |
|
Quartus® II software v14.1 specifications |
All |
14.1 |
|
Quartus® II software v14.0 specifications |
All |
14.0 |
|
Quartus® II software v13.1 specifications |
All |
13.1 |
|
Quartus® II software v13.0 SP1 specifications |
All |
13.0 SP1 |
Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
- Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.
- Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
- FPGA Developer Center - Contains resources to complete your Altera® FPGA design.