Optimization Support Resources
Design optimization can help you improve performance to reduce resource usage, close timing, and reduce compilation times. Support resources for design optimization, physical synthesis, and Design Space Explorer (DSE).
Intel® Quartus® Prime software includes a wide range of features to help you optimize your design for area and timing.
- Physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.
- DSE automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.
- The incremental optimization capability in the Intel® Quartus® Prime Design Software Pro Edition software offers a fast methodology to converge to design sign-off.
Table 1. Optimization Support Documentation
| User Guide Title | Chapter | Description |
|---|---|---|
| Intel® Quartus® Prime Pro Edition User Guides | Area Optimization | This chapter describes techniques to reduce resource usage when designing for Intel® devices. |
| Timing Closure and Optimization |
This chapter describes techniques to improve timing performance when designing for Intel FPGA devices. | |
| Analyzing and Optimizing the Design Floorplan |
Determining the layout (placement) of your design elements into physical resources on the FPGA device is known as floorplanning. | |
| Chip Planner GUI | The Chip Planner GUI helps you to visualize and modify the use of device resources for your design. As you zoom in, the level of abstraction decreases, revealing more details about your design. | |
| Netlist Optimizations and Physical Synthesis | The Intel® Quartus® Prime software offers netlist optimizations during synthesis, and physical synthesis optimization during fitting, that can improve the performance of your design. |
Table 2. Optimization Support Resources
Resource Centers |
Description |
|---|---|
Following recommended coding guidelines can be a powerful way to obtain good quality results. Refer to the Design and Coding Guidelines section in the Synthesis and Netlist Viewer Resource Center for more information. |
|
You can use incremental compilation to reduce compilation times and preserve results during optimization. |
Table 3. Optimization Support Training Courses and Demonstrations
Course Title |
Course Description |
|---|---|
| Beginner Intel® FPGA Designer | This learning plan will introduce you to the basics of FPGAs including their history, structure, and where they fit into the electronics industry. It will also give you the knowledge to complete your first FPGA design. |
Learn about the chip planner tasks, layers, and views, and how to perform design analysis with chip planner. See how to view critical paths and physical timing estimates. You will also see how to use chip planner to perform power analysis and to view routing congestion. You will also learn how to perform ECOs and to work with floorplan assignments. |
|
Timing Closure Using Quartus II Advisors and Design Space Explorer |
Learn how to use the Intel® Quartus® Prime Pro Design Space Explorer II (DSE) as an aid to remote and parallel compilation. |
| Learn how to address timing closure issues with HDL design techniques. |
Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
- Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.
- Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
- FPGA Developer Center - Contains resources to complete your Altera® FPGA design.