Synthesis and Netlist Viewers Resource Center
The Intel® Quartus® Prime and Quartus® II software includes advanced integrated synthesis and interfaces with other third-party synthesis tools. The software also offers schematic netlist viewers that you can use to analyze a design's structure and see how the software interpreted your design.
For a brief overview of synthesis features, refer to the Synthesis product page.
To search for known issues and technical support solutions related to synthesis or the netlist viewers, use Intel® FPGA’s Knowledge Database. You can also visit the Intel® FPGA Forum to connect and discuss technical issues with other Intel® FPGA users.
For further technical support, use mySupport to create, view, and update service requests.
Synthesis Resources
Table 1 provides links to available documentation on Intel Quartus Prime integrated synthesis and interfaces with third-party synthesis tools.
Table 1. Synthesis Documentation
Title |
Description |
|---|---|
This handbook chapter documents the design flow and language support in the Intel Quartus Prime software. It explains how to improve and control your synthesis results with Intel Quartus Prime synthesis options, attributes, and other features. It also discusses node-naming conventions and how to preserve nodes through synthesis. |
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This handbook chapter documents support for the Synplicity Synplify and Synplify Pro software in the Intel Quartus Prime software, as well as key design methodologies and techniques for achieving good results in Intel® FPGA devices. |
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This handbook chapter documents support for the Mentor Graphics Precision RTL Synthesis software in the Intel Quartus Prime software, as well as key design methodologies and techniques for achieving good results in Intel® FPGA devices. |
Table 2 provides links to available training and demonstrations on Quartus II integrated synthesis and interfaces with third-party synthesis tools.
Table 2. Synthesis Training and Demonstrations
Title |
Description |
|---|---|
Compilation |
You will see how to make settings in a project, start a compilation, and view your results. This is a 2.5-minute demonstration. |
Using the Quartus II Software: An Introduction |
You will become familiar with the basic Quartus II design environment. You will learn about the steps of the basic FPGA design flow and how to use Quartus II software in the flow. You will locate basic functions in the Quartus II software user interface, such as where to create new projects and how to make pin assignments, and where to locate Quartus II software compilation output information. This is a 1.5-hour online course. |
The Quartus II Software Interactive Tutorial |
This interactive tutorial teaches you the basic components of the Quartus II design software including best-practice design flows, project management and design tools, and programming a device with your tested design. Each tutorial module has a Show Me, Guide Me, & Test Me component to first achieve an understanding of a design feature and then test you on what you have learned. You can navigate to any module in the tutorial at any time using the Table of Contents, and explore features at your own pace. This is a 4-hour online interactive tutorial course. |
The Quartus II Software Design Series: Foundation The Quartus II Software Design Series: Foundation |
You will create a new project, enter in new or existing design files, compile, and configure your device using the programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the TimeQuest timing analyzer. You will also learn how to plan and manage pin assignments and will discover how the software interfaces with common EDA tools used for synthesis and simulation. This is a 1-day instructor-led course or 8-hour online course. |
Netlist Viewers Resources
Table 3 provides a link to available documentation on the Quartus II netlist viewers.
Table 3. Netlist Viewers Documentation
Resource |
Description |
|---|---|
This handbook chapter describes the user interface and features of the viewers and provides examples. The RTL viewer, state machine viewer, and technology map viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, or constraint entry process. |
Table 4 provides links to available training and demonstrations on the Quartus II netlist viewers.
Table 4. Netlist Viewers Training and Demonstrations
Resource |
Description |
|---|---|
Using the RTL Viewer and Technology Map Viewer to Check Synthesis and Fitting Results |
You will see how to navigate in the RTL and technology map viewers and how you can use the viewers to debug design problems. This is a 5-minute demonstration. |
Design Optimization Using Quartus II Incremental Compilation |
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle, as well as improve your design performance and utilization. This is a 1-day instructor-led course. |