An ASCII text file (with the extension .v, .verilog, .vlg, or .vh) created with the Quartus® Prime Standard Edition Text Editor or any other standard text editor. A Verilog Design File contains design logic that is defined with Verilog HDL.
A Verilog Design File can contain any combination of the Verilog HDL constructs supported by the Quartus® Prime Standard Edition software. For more information, see "Quartus® Prime Standard Edition Verilog HDL Support."