SystemVerilog Design File (.sv) Definition

An ASCII text file (with the extension .sv) created with the Quartus® Prime Standard Edition Text Editor or any other standard text editor. A SystemVerilog Design File describes design logic in the SystemVerilog language, which is an extension to Verilog.

A SystemVerilog Design File can contain any combination of the SystemVerilog constructs supported by the Quartus® Prime Standard Edition software. For more information, see "Quartus® Prime Standard Edition Support for SystemVerilog 2005."

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