noc_fw_ddr_mpu_fpga2sdram_ddr_scr Summary

Base Address: 0xFFD13300

Register

Address Offset

Bit Fields
noc_fw_ddr_mpu_fpga2sdram_ddr_scr

enable

0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fpga2sdram2region3enable

RW 0x0

fpga2sdram2region2enable

RW 0x0

fpga2sdram2region1enable

RW 0x0

fpga2sdram2region0enable

RW 0x0

fpga2sdram1region3enable

RW 0x0

fpga2sdram1region2enable

RW 0x0

fpga2sdram1region1enable

RW 0x0

fpga2sdram1region0enable

RW 0x0

fpga2sdram0region3enable

RW 0x0

fpga2sdram0region2enable

RW 0x0

fpga2sdram0region1enable

RW 0x0

fpga2sdram0region0enable

RW 0x0

mpuregion3enable

RW 0x0

mpuregion2enable

RW 0x0

mpuregion1enable

RW 0x0

mpuregion0enable

RW 0x0

enable_set

0x4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fpga2sdram2region3enable

WO 0x0

fpga2sdram2region2enable

WO 0x0

fpga2sdram2region1enable

WO 0x0

fpga2sdram2region0enable

WO 0x0

fpga2sdram1region3enable

WO 0x0

fpga2sdram1region2enable

WO 0x0

fpga2sdram1region1enable

WO 0x0

fpga2sdram1region0enable

WO 0x0

fpga2sdram0region3enable

WO 0x0

fpga2sdram0region2enable

WO 0x0

fpga2sdram0region1enable

WO 0x0

fpga2sdram0region0enable

WO 0x0

mpuregion3enable

WO 0x0

mpuregion2enable

WO 0x0

mpuregion1enable

WO 0x0

mpuregion0enable

WO 0x0

enable_clear

0x8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fpga2sdram2region3enable

WO 0x0

fpga2sdram2region2enable

WO 0x0

fpga2sdram2region1enable

WO 0x0

fpga2sdram2region0enable

WO 0x0

fpga2sdram1region3enable

WO 0x0

fpga2sdram1region2enable

WO 0x0

fpga2sdram1region1enable

WO 0x0

fpga2sdram1region0enable

WO 0x0

fpga2sdram0region3enable

WO 0x0

fpga2sdram0region2enable

WO 0x0

fpga2sdram0region1enable

WO 0x0

fpga2sdram0region0enable

WO 0x0

mpuregion3enable

WO 0x0

mpuregion2enable

WO 0x0

mpuregion1enable

WO 0x0

mpuregion0enable

WO 0x0

mpuregion0addr

0x10

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

mpuregion1addr

0x14

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

mpuregion2addr

0x18

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

mpuregion3addr

0x1C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram0region0addr

0x20

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram0region1addr

0x24

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram0region2addr

0x28

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram0region3addr

0x2C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram1region0addr

0x30

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram1region1addr

0x34

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram1region2addr

0x38

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram1region3addr

0x3C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram2region0addr

0x40

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram2region1addr

0x44

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram2region2addr

0x48

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram2region3addr

0x4C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0