enable
Enable
| Module Instance | Base Address | Register Address |
|---|---|---|
| noc_fw_ddr_mpu_fpga2sdram_ddr_scr | 0xFFD13300 | 0xFFD13300 |
Offset: 0x0
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
fpga2sdram2region3enable RW 0x0 |
fpga2sdram2region2enable RW 0x0 |
fpga2sdram2region1enable RW 0x0 |
fpga2sdram2region0enable RW 0x0 |
fpga2sdram1region3enable RW 0x0 |
fpga2sdram1region2enable RW 0x0 |
fpga2sdram1region1enable RW 0x0 |
fpga2sdram1region0enable RW 0x0 |
fpga2sdram0region3enable RW 0x0 |
fpga2sdram0region2enable RW 0x0 |
fpga2sdram0region1enable RW 0x0 |
fpga2sdram0region0enable RW 0x0 |
mpuregion3enable RW 0x0 |
mpuregion2enable RW 0x0 |
mpuregion1enable RW 0x0 |
mpuregion0enable RW 0x0 |
enable Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15 | fpga2sdram2region3enable | FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 14 | fpga2sdram2region2enable | FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 13 | fpga2sdram2region1enable | FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 12 | fpga2sdram2region0enable | FPGA2SDRAM2 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 11 | fpga2sdram1region3enable | FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 10 | fpga2sdram1region2enable | FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 9 | fpga2sdram1region1enable | FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 8 | fpga2sdram1region0enable | FPGA2SDRAM1 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 7 | fpga2sdram0region3enable | FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 6 | fpga2sdram0region2enable | FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 5 | fpga2sdram0region1enable | FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 4 | fpga2sdram0region0enable | FPGA2SDRAM0 Region Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 3 | mpuregion3enable | MPU Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 2 | mpuregion2enable | MPU Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 1 | mpuregion1enable | MPU Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |
| 0 | mpuregion0enable | MPU Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled |
RW | 0x0 |