enable_clear

         Clears Master Region Enable field when written with 1
Module Instance Base Address Register Address
noc_fw_ddr_mpu_fpga2sdram_ddr_scr 0xFFD13300 0xFFD13308

Offset: 0x8

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fpga2sdram2region3enable

WO 0x0

fpga2sdram2region2enable

WO 0x0

fpga2sdram2region1enable

WO 0x0

fpga2sdram2region0enable

WO 0x0

fpga2sdram1region3enable

WO 0x0

fpga2sdram1region2enable

WO 0x0

fpga2sdram1region1enable

WO 0x0

fpga2sdram1region0enable

WO 0x0

fpga2sdram0region3enable

WO 0x0

fpga2sdram0region2enable

WO 0x0

fpga2sdram0region1enable

WO 0x0

fpga2sdram0region0enable

WO 0x0

mpuregion3enable

WO 0x0

mpuregion2enable

WO 0x0

mpuregion1enable

WO 0x0

mpuregion0enable

WO 0x0

enable_clear Fields

Bit Name Description Access Reset
15 fpga2sdram2region3enable 
FPGA2SDRAM2 Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram2region3enable bit to zero
 WO 0x0
14 fpga2sdram2region2enable 
FPGA2SDRAM2 Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram2region2enable bit to zero
 WO 0x0
13 fpga2sdram2region1enable 
FPGA2SDRAM2 Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram2region1enable bit to zero
 WO 0x0
12 fpga2sdram2region0enable 
FPGA2SDRAM2 Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram2region0enable bit to zero
 WO 0x0
11 fpga2sdram1region3enable 
FPGA2SDRAM1 Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram1region3enable bit to zero
 WO 0x0
10 fpga2sdram1region2enable 
FPGA2SDRAM1 Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram1region2enable bit to zero
 WO 0x0
9 fpga2sdram1region1enable 
FPGA2SDRAM1 Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram1region1enable bit to zero
 WO 0x0
8 fpga2sdram1region0enable 
FPGA2SDRAM1 Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram1region0enable bit to zero
 WO 0x0
7 fpga2sdram0region3enable 
FPGA2SDRAM0 Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram0region3enable bit to zero
 WO 0x0
6 fpga2sdram0region2enable 
FPGA2SDRAM0 Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram0region2enable bit to zero
 WO 0x0
5 fpga2sdram0region1enable 
FPGA2SDRAM0 Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram0region1enable bit to zero
 WO 0x0
4 fpga2sdram0region0enable 
FPGA2SDRAM0 Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the fpga2sdram0region0enable bit to zero
 WO 0x0
3 mpuregion3enable 
MPU Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the mpuregion3enable bit to zero
 WO 0x0
2 mpuregion2enable 
MPU Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the mpuregion2enable bit to zero
 WO 0x0
1 mpuregion1enable 
MPU Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the mpuregion1enable bit to zero
 WO 0x0
0 mpuregion0enable 
MPU Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the mpuregion0enable bit to zero
 WO 0x0