fpga2sdram2region3addr

         Base and Limit definition for FPGA2SDRAM2 Region 3
Module Instance Base Address Register Address
noc_fw_ddr_mpu_fpga2sdram_ddr_scr 0xFFD13300 0xFFD1334C

Offset: 0x4C

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

limit

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

base

RW 0x0

fpga2sdram2region3addr Fields

Bit Name Description Access Reset
31:16 limit 
Limit defines the 16 bit MSB of the address field. Remaining LSB field is all ones. Region end address is {limit, 16'hFFF}
 RW 0x0
15:0 base 
Base defines the 16 bit MSB of the address field. Remaining LSB field is all zeros. Region start address is {base, 16'h000}
 RW 0x0