clkmgr_clkmgrp Address Map

Module Instance	Base Address	End Address
`i_clk_mgr_clkmgr`	`0xFFD04000`	`0xFFD0403F`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`ctrl`	`0x0`	`32`	`RW`	`0x3`	Control Register
`intr`	`0x4`	`32`	`RW`	`0x0`	Interrupt Status Register
`intrs`	`0x8`	`32`	`RW`	`0x0`	Interrupt Status Register Set
`intrr`	`0xC`	`32`	`RW`	`0x0`	Interrupt Status Register Reset
`intren`	`0x10`	`32`	`RW`	`0x0`	Interrupt Enable Register
`intrens`	`0x14`	`32`	`RW`	`0x0`	Interrupt Enable Register Set
`intrenr`	`0x18`	`32`	`RW`	`0x0`	Interrupt Enable Register Reset
`stat`	`0x1C`	`32`	`RO`	`0x10000`	Status Register
`testioctrl`	`0x20`	`32`	`RW`	`0x100808`	Test IO Control Register