stat
Provides status for Clock Manager including PLL lock and HW Managed Clock State Machine busy.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_clk_mgr_clkmgr | 0xFFD04000 | 0xFFD0401C |
Offset: 0x1C
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
bootclksrc RO 0x0 |
bootmode RO 0x1 |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
perplllocked RO 0x0 |
mainplllocked RO 0x0 |
Reserved |
busy RO 0x0 |
|||||||||||
stat Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 17 | bootclksrc | If 1, the source of boot_clk is cb_intosc_hs_div2_clk. . If 0, the boot_clk source is the external oscillator (HPS_CLK1 input pin which becomes signal osc1_clk in the device). This is a read only status. |
RO | 0x0 | ||||||
| 16 | bootmode | If 1, the clocks are currently in Boot Mode. If 0, the clocks are not in Boot Mode. This is a read only status. For SW to exit Boot Mode, SW must clear the RW bit CTRL.BOOTMODE. |
RO | 0x1 | ||||||
| 9 | perplllocked | If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is currently not locked. |
RO | 0x0 | ||||||
| 8 | mainplllocked | If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not locked. |
RO | 0x0 | ||||||
| 0 | busy | This read only bit indicates that the Hardware Managed clock's state machine is active. If the state machine is active, then the clocks are in transition. Software should poll this bit after changing the source of internal clocks when changing the state of CTRL.BOOTMODE, MAINPLLGRP.BYPASS.MPU or MAINPLLGRP.BYPASS.NOC register bits. Immediately following writes to any of these registers, SW should wait 0.5 usecs and then poll this BUSY bit until it is IDLE before proceeding with any other register writes in the Clock Manager. The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.
|
RO | 0x0 |