intren

         Contain fields that enable the interrupt
Module Instance Base Address Register Address
i_clk_mgr_clkmgr 0xFFD04000 0xFFD04010

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

perpllfbslip

RW 0x0

mainpllfbslip

RW 0x0

perpllrfslip

RW 0x0

mainpllrfslip

RW 0x0

Reserved

perplllost

RW 0x0

mainplllost

RW 0x0

perpllachieved

RW 0x0

mainpllachieved

RW 0x0

intren Fields

Bit Name Description Access Reset
11 perpllfbslip 
When set to 1,the Peripheral PLL feedback cycle slipped bit is ORed into the Clock Manager interrupt output.  When set to 0, the Peripheral PLL feedback cylce slipped bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
10 mainpllfbslip 
When set to 1,the Main PLL feedback cycle slipped bit is ORed into the Clock Manager interrupt output.  When set to 0, the Main PLL feedback cylce slipped bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
9 perpllrfslip 
When set to 1,the Peripheral PLL reference cycle slipped bit is ORed into the Clock Manager interrupt output.  When set to 0, the Peripheral PLL reference cylce slipped bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
8 mainpllrfslip 
When set to 1,the Main PLL reference cycle slipped bit is ORed into the Clock Manager interrupt output.  When set to 0, the Main PLL reference cylce slipped bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
3 perplllost 
When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager interrupt output.  When set to 0 the Peripheral PLL lost lock bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
2 mainplllost 
When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager interrupt output.  When set to 0 the Main PLL lost lock bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
1 perpllachieved 
When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock Manager interrupt output.  When set to 0 the Peripheral PLL achieved lock bit is not ORed into the Clock Manager interrupt output.
 RW 0x0
0 mainpllachieved 
When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager interrupt output.  When set to 0 the Main PLL achieved lock bit is not ORed into the Clock Manager interrupt output.
 RW 0x0