intrr

         Contains fields that indicate the PLL lock status.
      
Module Instance Base Address Register Address
i_clk_mgr_clkmgr 0xFFD04000 0xFFD0400C

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

perpllfbslip

RW 0x0

mainpllfbslip

RW 0x0

perpllrfslip

RW 0x0

mainpllrfslip

RW 0x0

Reserved

perplllost

RW 0x0

mainplllost

RW 0x0

perpllachieved

RW 0x0

mainpllachieved

RW 0x0

intrr Fields

Bit Name Description Access Reset
11 perpllfbslip
If 1, the Peripheral PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.
RW 0x0
10 mainpllfbslip
If 1, the Main PLL feedback cycle has slipped (CLKOUT frequency too low).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.
RW 0x0
9 perpllrfslip
If 1, the Peripheral PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.
RW 0x0
8 mainpllrfslip
If 1, the Main PLL reference cycle has slipped (CLKOUT frequency too high).  This does not mean the PLL has lost lock, but the quality of the clock has degraded.
RW 0x0
3 perplllost
If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared.
RW 0x0
2 mainplllost
If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, the Main PLL has not lost lock since this bit was cleared.
RW 0x0
1 perpllachieved
If 1, the Peripheral PLL has achieved lock at least once since this bit was cleared. If 0, the Peripheral PLL has not achieved lock since this bit was cleared.
RW 0x0
0 mainpllachieved
If 1, the Main PLL has achieved lock at least once since this bit was cleared. If 0, the Main PLL has not achieved lock since this bit was cleared.
RW 0x0