uart Address Map

Module Instance Base Address End Address
i_uart_0_uart 0xFFC02000 0xFFC020FF
i_uart_1_uart 0xFFC02100 0xFFC021FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
rbr_thr_dll 0x0 32 RW 0x0 
Rx Buffer, Tx Holding, and Divisor Latch Low
ier_dlh 0x4 32 RW 0x0 
Interrupt Enable and Divisor Latch High
iir 0x8 32 RO 0x1 
Interrupt Identification Register
fcr 0x8 32 WO 0x0 
FIFO Control Register
lcr 0xC 32 RW 0x0 
Line Control Register
mcr 0x10 32 RW 0x0 
Modem Control Register
lsr 0x14 32 RO 0x60 
Line Status Register
msr 0x18 32 RO 0x0 
Modem Status Register
It should be noted that whenever bits 0, 1, 2 or 3 is set to logic one, to indicate
a change on the modem control inputs, a modem status interrupt will be generated
if enabled via the IER regardless of when the change occurred. Since the delta bits
(bits 0, 1, 3) can get set after a reset if their respective modem signals are
active (see individual bits for details), a read of the MSR after reset can be
performed to prevent unwanted interrupts.
scr 0x1C 32 RW 0x0 
Scratchpad Register
srbr_sthr_0 0x30 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_1 0x34 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_2 0x38 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_3 0x3C 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_4 0x40 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_5 0x44 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_6 0x48 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_7 0x4C 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_8 0x50 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_9 0x54 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_10 0x58 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_11 0x5C 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_12 0x60 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_13 0x64 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_14 0x68 32 RW 0x0 
Shadow RBR and THR
srbr_sthr_15 0x6C 32 RW 0x0 
Shadow RBR and THR
far 0x70 32 RW 0x0 
FIFO Access Register
tfr 0x74 32 RO 0x0 
Transmit FIFO Read
rfw 0x78 32 RW 0x0 
Receive FIFO Write
usr 0x7C 32 RO 0x6 
UART Status register.
tfl 0x80 32 RO 0x0 





rfl
0x84
32
RO
0x0

Receive FIFO Level.





srr
0x88
32
RW
0x0

Software Reset Register.





srts
0x8C
32
RW
0x0

Shadow Request to Send.





sbcr
0x90
32
RW
0x0

Shadow Break Control Register.





sdmam
0x94
32
RW
0x0

Shadow DMA Mode.





sfe
0x98
32
RW
0x0

Shadow FIFO Enable





srt
0x9C
32
RW
0x0

Shadow RCVR Trigger





stet
0xA0
32
RW
0x0

Shadow TX Empty Trigger





htx
0xA4
32
RW
0x0

Halt TX





dmasa
0xA8
32
RW
0x0

DMA Software Acknowledge





cpr
0xF4
32
RO
0x83F32

Component Parameter Register





ucv
0xF8
32
RO
0x3331342A

Component Version





ctr
0xFC
32
RO
0x44570110

Component Type Register