dmasa

         DMA Software Acknowledge

Module Instance	Base Address	Register Address
`i_uart_0_uart`	`0xFFC02000`	`0xFFC020A8`
`i_uart_1_uart`	`0xFFC02100`	`0xFFC021A8`

Offset: 0xA8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rsvd_dmasa_31to1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rsvd_dmasa_31to1` `RO 0x0`															`dmasa` `WO 0x0`

dmasa Fields

Bit	Name	Description	Access	Reset
31:1	`rsvd_dmasa_31to1`	Reserved bits [31:1] - Read Only	`RO`	`0x0`
0	`dmasa`	DMA Software Acknowledge. Writes will have no effect when DMA_EXTRA == No. This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit.	`WO`	`0x0`

Bit

Name

Description

Access

Reset

31:1

rsvd_dmasa_31to1

Reserved bits [31:1] - Read Only

RO

0x0

dmasa

DMA Software Acknowledge.
Writes will have no effect when DMA_EXTRA == No.  This register is use to perform
DMA software acknowledge if a transfer needs to be terminated due to an error
condition. For example, if the DMA disables the channel, then the DW_apb_uart should
clear its request. This will cause the TX request, TX single, RX request and RX
single signals to de-assert.
Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

WO

0x0