htx

         Halt TX
      
Module Instance Base Address Register Address
i_uart_0_uart 0xFFC02000 0xFFC020A4
i_uart_1_uart 0xFFC02100 0xFFC021A4

Offset: 0xA4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_htx_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_htx_31to1

RO 0x0

htx

RW 0x0

htx Fields

Bit Name Description Access Reset
31:1 rsvd_htx_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 htx
Halt TX.
Writes will have no effect when FIFO_MODE == NONE, always readable.  This register
is use to halt transmissions for testing, so that the transmit FIFO can be filled
by the master when FIFO's are implemented and enabled.
Note, if FIFO's are implemented and not enabled the setting of the halt TX register
will have no effect on operation.
0 = Halt TX disabled
1 = Halt TX enabled
Value Description
0 DISABLED
1 ENABLED
RW 0x0