SDMMC Summary

Block

Base Address: 0xFF808000

Register Address Offset	Bit Fields
`i_sdmmc_sdmmc_block_0`
`CTRL` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`						`USE_INTERNAL_DMAC` `RW 0x0`	`ENABLE_OD_PULLUP` `RW 0x0`	`CARD_VOLTAGE_B` `RW 0x0`				`CARD_VOLTAGE_A` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`CEATA_DEVICE_INTERRUPT_STATUS` `RW 0x0`	`SEND_AUTO_STOP_CCSD` `RW 0x0`	`SEND_CCSD` `RW 0x0`	`ABORT_READ_DATA` `RW 0x0`	`SEND_IRQ_RESPONSE` `RW 0x0`	`READ_WAIT` `RW 0x0`	`DMA_ENABLE` `RW 0x0`	`INT_ENABLE` `RW 0x0`	`Reserved`	`DMA_RESET` `RW 0x0`	`FIFO_RESET` `RW 0x0`	`CONTROLLER_RESET` `RW 0x0`
`PWREN` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`POWER_ENABLE_0` `RW 0x0`
`CLKDIV` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CLK_DIVIDER3` `RO 0x0`								`CLK_DIVIDER2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CLK_DIVIDER1` `RO 0x0`								`CLK_DIVIDER0` `RW 0x0`
`CLKSRC` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CARD15_CLK_SOURCE` `RO 0x0`		`CARD14_CLK_SOURCE` `RO 0x0`		`CARD13_CLK_SOURCE` `RO 0x0`		`CARD12_CLK_SOURCE` `RO 0x0`		`CARD11_CLK_SOURCE` `RO 0x0`		`CARD10_CLK_SOURCE` `RO 0x0`		`CARD9_CLK_SOURCE` `RO 0x0`		`CARD8_CLK_SOURCE` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CARD7_CLK_SOURCE` `RO 0x0`		`CARD6_CLK_SOURCE` `RO 0x0`		`CARD5_CLK_SOURCE` `RO 0x0`		`CARD4_CLK_SOURCE` `RO 0x0`		`CARD3_CLK_SOURCE` `RO 0x0`		`CARD2_CLK_SOURCE` `RO 0x0`		`CARD1_CLK_SOURCE` `RO 0x0`		`CARD0_CLK_SOURCE` `RO 0x0`
`CLKENA` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`CCLK_LOW_POWER_0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`CCLK_ENABLE_0` `RW 0x0`
`TMOUT` `0x14` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DATA_TIMEOUT` `RW 0xFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DATA_TIMEOUT` `RW 0xFFFFFF`								`RESPONSE_TIMEOUT` `RW 0x40`
`CTYPE` `0x18` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`CARD0_WIDTH1` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`CARD0_WIDTH2` `RW 0x0`
`BLKSIZ` `0x1C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BLOCK_SIZE` `RW 0x200`
`BYTCNT` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BYTE_COUNT` `RW 0x200`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BYTE_COUNT` `RW 0x200`
`INTMASK` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SDIO_INT_MASK_CARD15` `RW 0x0`	`SDIO_INT_MASK_CARD14` `RW 0x0`	`SDIO_INT_MASK_CARD13` `RW 0x0`	`SDIO_INT_MASK_CARD12` `RW 0x0`	`SDIO_INT_MASK_CARD11` `RW 0x0`	`SDIO_INT_MASK_CARD10` `RW 0x0`	`SDIO_INT_MASK_CARD9` `RW 0x0`	`SDIO_INT_MASK_CARD8` `RW 0x0`	`SDIO_INT_MASK_CARD7` `RW 0x0`	`SDIO_INT_MASK_CARD6` `RW 0x0`	`SDIO_INT_MASK_CARD5` `RW 0x0`	`SDIO_INT_MASK_CARD4` `RW 0x0`	`SDIO_INT_MASK_CARD3` `RW 0x0`	`SDIO_INT_MASK_CARD2` `RW 0x0`	`SDIO_INT_MASK_CARD1` `RW 0x0`	`SDIO_INT_MASK_CARD0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`EBE_INT_MASK` `RW 0x0`	`ACD_INT_MASK` `RW 0x0`	`SBE_BCI_INT_MASK` `RW 0x0`	`HLE_INT_MASK` `RW 0x0`	`FRUN_INT_MASK` `RW 0x0`	`HTO_INT_MASK` `RW 0x0`	`DRTO_INT_MASK` `RW 0x0`	`RTO_INT_MASK` `RW 0x0`	`DCRC_INT_MASK` `RW 0x0`	`RCRC_INT_MASK` `RW 0x0`	`RXDR_INT_MASK` `RW 0x0`	`TXDR_INT_MASK` `RW 0x0`	`DTO_INT_MASK` `RW 0x0`	`CMD_INT_MASK` `RW 0x0`	`RE_INT_MASK` `RW 0x0`	`CD_INT_MASK` `RW 0x0`
`CMDARG` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CMD_ARG` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CMD_ARG` `RW 0x0`
`CMD` `0x2C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`START_CMD` `RW 0x0`	`Reserved`	`USE_HOLD_REG` `RW 0x1`	`VOLT_SWITCH` `RW 0x0`	`BOOT_MODE` `RW 0x0`	`DISABLE_BOOT` `RW 0x0`	`EXPECT_BOOT_ACK` `RW 0x0`	`ENABLE_BOOT` `RW 0x0`	`CCS_EXPECTED` `RW 0x0`	`READ_CEATA_DEVICE` `RW 0x0`	`UPDATE_CLOCK_REGISTERS_ONLY` `RW 0x0`	`CARD_NUMBER` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SEND_INITIALIZATION` `RW 0x0`	`STOP_ABORT_CMD` `RW 0x0`	`WAIT_PRVDATA_COMPLETE` `RW 0x0`	`SEND_AUTO_STOP` `RW 0x0`	`TRANSFER_MODE` `RW 0x0`	`READ_WRITE` `RW 0x0`	`DATA_EXPECTED` `RW 0x0`	`CHECK_RESPONSE_CRC` `RW 0x0`	`RESPONSE_LENGTH` `RW 0x0`	`RESPONSE_EXPECT` `RW 0x0`	`CMD_INDEX` `RW 0x0`
`RESP0` `0x30` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESPONSE0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE0` `RO 0x0`
`RESP1` `0x34` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESPONSE1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE1` `RO 0x0`
`RESP2` `0x38` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESPONSE2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE2` `RO 0x0`
`RESP3` `0x3C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RESPONSE3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE3` `RO 0x0`
`MINTSTS` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SDIO_INTERRUPT_CARD15` `RO 0x0`	`SDIO_INTERRUPT_CARD14` `RO 0x0`	`SDIO_INTERRUPT_CARD13` `RO 0x0`	`SDIO_INTERRUPT_CARD12` `RO 0x0`	`SDIO_INTERRUPT_CARD11` `RO 0x0`	`SDIO_INTERRUPT_CARD10` `RO 0x0`	`SDIO_INTERRUPT_CARD9` `RO 0x0`	`SDIO_INTERRUPT_CARD8` `RO 0x0`	`SDIO_INTERRUPT_CARD7` `RO 0x0`	`SDIO_INTERRUPT_CARD6` `RO 0x0`	`SDIO_INTERRUPT_CARD5` `RO 0x0`	`SDIO_INTERRUPT_CARD4` `RO 0x0`	`SDIO_INTERRUPT_CARD3` `RO 0x0`	`SDIO_INTERRUPT_CARD2` `RO 0x0`	`SDIO_INTERRUPT_CARD1` `RO 0x0`	`SDIO_INTERRUPT_CARD0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`END_BIT_ERROR_INTERRUPT` `RO 0x0`	`AUTO_COMMAND_DONE_INTERRUPT` `RO 0x0`	`BUSY_COMPLETE_INTERRUPT_INTERRUPT` `RO 0x0`	`HARDWARE_LOCKED_WRITE_INTERRUPT` `RO 0x0`	`FIFO_UNDER_OVER_RUN_INTERRUPT` `RO 0x0`	`HOST_TIMEOUT_INTERRUPT` `RO 0x0`	`DATA_READ_TIMEOUT_INTERRUPT` `RO 0x0`	`RESPONSE_TIMEOUT_INTERRUPT` `RO 0x0`	`DATA_CRC_ERROR_INTERRUPT` `RO 0x0`	`RESPONSE_CRC_ERROR_INTERRUPT` `RO 0x0`	`RECEIVE_FIFO_DATA_REQUEST_INTERRUPT` `RO 0x0`	`TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT` `RO 0x0`	`DATA_TRANSFER_OVER_INTERRUPT` `RO 0x0`	`COMMAND_DONE_INTERRUPT` `RO 0x0`	`RESPONSE_ERROR_INTERRUPT` `RO 0x0`	`CARD_DETECT_INTERRUPT` `RO 0x0`
`RINTSTS` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SDIO_INTERRUPT_CARD15` `RW 0x0`	`SDIO_INTERRUPT_CARD14` `RW 0x0`	`SDIO_INTERRUPT_CARD13` `RW 0x0`	`SDIO_INTERRUPT_CARD12` `RW 0x0`	`SDIO_INTERRUPT_CARD11` `RW 0x0`	`SDIO_INTERRUPT_CARD10` `RW 0x0`	`SDIO_INTERRUPT_CARD9` `RW 0x0`	`SDIO_INTERRUPT_CARD8` `RW 0x0`	`SDIO_INTERRUPT_CARD7` `RW 0x0`	`SDIO_INTERRUPT_CARD6` `RW 0x0`	`SDIO_INTERRUPT_CARD5` `RW 0x0`	`SDIO_INTERRUPT_CARD4` `RW 0x0`	`SDIO_INTERRUPT_CARD3` `RW 0x0`	`SDIO_INTERRUPT_CARD2` `RW 0x0`	`SDIO_INTERRUPT_CARD1` `RW 0x0`	`SDIO_INTERRUPT_CARD0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`END_BIT_ERROR_STATUS` `RW 0x0`	`AUTO_COMMAND_DONE_STATUS` `RW 0x0`	`BUSY_COMPLETE_STATUS` `RW 0x0`	`HARDWARE_LOCKED_WRITE_STATUS` `RW 0x0`	`FIFO_UNDER_OVER_RUN_STATUS` `RW 0x0`	`HOST_TIMEOUT_STATUS` `RW 0x0`	`DATA_READ_TIMEOUT_STATUS` `RW 0x0`	`RESPONSE_TIMEOUT_STATUS` `RW 0x0`	`DATA_CRC_ERROR_STATUS` `RW 0x0`	`RESPONSE_CRC_ERROR_STATUS` `RW 0x0`	`RECEIVE_FIFO_DATA_REQUEST_STATUS` `RW 0x0`	`TRANSMIT_RECEIVE_FIFO_DATA_STATUS` `RW 0x0`	`DATA_TRANSFER_OVER_STATUS` `RW 0x0`	`COMMAND_DONE_STATUS` `RW 0x0`	`RESPONSE_ERROR_STATUS` `RW 0x0`	`CARD_DETECT_STATUS` `RW 0x0`
`STATUS` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DMA_REQ` `RO 0x0`	`DMA_ACK` `RO 0x0`	`FIFO_COUNT` `RO 0x0`													`RESPONSE_INDEX` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RESPONSE_INDEX` `RO 0x0`					`DATA_STATE_MC_BUSY` `RO 0x0`	`DATA_BUSY` `RO 0x0`	`DATA_3_STATUS` `RO 0x1`	`COMMAND_FSM_STATES` `RO 0x0`				`FIFO_FULL` `RO 0x0`	`FIFO_EMPTY` `RO 0x1`	`FIFO_TX_WATERMARK` `RO 0x1`	`FIFO_RX_WATERMARK` `RO 0x0`
`FIFOTH` `0x4C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`	`DW_DMA_Multiple_Transaction_Size` `RW 0x0`			`RX_WMark` `RW 0x3FF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`TX_WMark` `RW 0x0`
`CDETECT` `0x50` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`CARD0_DETECT_N` `RO 0x1`
`WRTPRT` `0x54` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`WRITE_PROTECT_0` `RO 0x1`
`GPIO` `0x58` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`GPO` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`GPO` `RW 0x0`								`GPI` `RO 0x0`
`TCBCNT` `0x5C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TRANS_CARD_BYTE_COUNT` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TRANS_CARD_BYTE_COUNT` `RO 0x0`
`TBBCNT` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`TRANS_FIFO_BYTE_COUNT` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`TRANS_FIFO_BYTE_COUNT` `RO 0x0`
`DEBNCE` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`DEBOUNCE_COUNT` `RW 0xFFFFFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`DEBOUNCE_COUNT` `RW 0xFFFFFF`
`USRID` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`USR_ID` `RW 0x7967797`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`USR_ID` `RW 0x7967797`
`VERID` `0x6C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`VER_ID` `RO 0x5342280A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VER_ID` `RO 0x5342280A`
`HCON` `0x70` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`				`ADDR_CONFIG` `RO 0x0`	`AREA_OPT` `RO 0x0`	`NUM_CLK_DIC` `RO 0x0`		`FALSE_PATH` `RO 0x1`	`HOLD_REG` `RO 0x1`	`FIFO_RAM_IN` `RO 0x0`	`GE_DMA_DATA_WIDTH` `RO 0x1`			`DMA_IF` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`H_ADDR_WIDTH` `RO 0xC`						`H_DATA_WIDTH` `RO 0x1`			`BUS_TYPE` `RO 0x0`	`NUM_CARD` `RO 0x0`					`CARD_TYPE` `RO 0x1`
`UHS_REG` `0x74` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`DDR_REG_15` `RW 0x0`	`DDR_REG_14` `RW 0x0`	`DDR_REG_13` `RW 0x0`	`DDR_REG_12` `RW 0x0`	`DDR_REG_11` `RW 0x0`	`DDR_REG_10` `RW 0x0`	`DDR_REG_9` `RW 0x0`	`DDR_REG_8` `RW 0x0`	`DDR_REG_7` `RW 0x0`	`DDR_REG_6` `RW 0x0`	`DDR_REG_5` `RW 0x0`	`DDR_REG_4` `RW 0x0`	`DDR_REG_3` `RW 0x0`	`DDR_REG_2` `RW 0x0`	`DDR_REG_1` `RW 0x0`	`DDR_REG_0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VOLT_REG_15` `RW 0x0`	`VOLT_REG_14` `RW 0x0`	`VOLT_REG_13` `RW 0x0`	`VOLT_REG_12` `RW 0x0`	`VOLT_REG_11` `RW 0x0`	`VOLT_REG_10` `RW 0x0`	`VOLT_REG_9` `RW 0x0`	`VOLT_REG_8` `RW 0x0`	`VOLT_REG_7` `RW 0x0`	`VOLT_REG_6` `RW 0x0`	`VOLT_REG_5` `RW 0x0`	`VOLT_REG_4` `RW 0x0`	`VOLT_REG_3` `RW 0x0`	`VOLT_REG_2` `RW 0x0`	`VOLT_REG_1` `RW 0x0`	`VOLT_REG_0` `RW 0x0`
`RST_n` `0x78` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`CARD0_RESET` `RW 0x1`
`BMOD` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`					`PBL` `RO 0x0`			`DE` `RW 0x0`	`DSL` `RW 0x0`					`FB` `RW 0x0`	`SWR` `RW 0x0`
`PLDMND` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`PD` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`PD` `WO 0x0`
`DBADDR` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SDL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SDL` `RW 0x0`
`IDSTS` `0x8C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`FSM` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FSM` `RO 0x0`			`EB` `RO 0x0`			`AIS` `RW 0x0`	`NIS` `RW 0x0`	`Reserved`		`CES` `RW 0x0`	`DU` `RW 0x0`	`Reserved`	`FBE` `RW 0x0`	`RI` `RW 0x0`	`TI` `RW 0x0`
`IDINTEN` `0x90` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`AI` `RW 0x0`	`NI` `RW 0x0`	`Reserved`		`CES` `RW 0x0`	`DU` `RW 0x0`	`Reserved`	`FBE` `RW 0x0`	`RI` `RW 0x0`	`TI` `RW 0x0`
`DSCADDR` `0x94` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`HDA` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HDA` `RO 0x0`
`BUFADDR` `0x98` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`HBA` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`HBA` `RO 0x0`
`CARDTHRCTL` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`			`CARDRDTHRESHOLD` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`CARDWRTHREN` `RO 0x0`	`BUSY_CLR_INT_EN` `RW 0x0`	`CARDRDTHREN` `RW 0x0`
`BACK_END_POWER_R` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BACK_END_POWER_15` `RW 0x0`	`BACK_END_POWER_14` `RW 0x0`	`BACK_END_POWER_13` `RW 0x0`	`BACK_END_POWER_12` `RW 0x0`	`BACK_END_POWER_11` `RW 0x0`	`BACK_END_POWER_10` `RW 0x0`	`BACK_END_POWER_9` `RW 0x0`	`BACK_END_POWER_8` `RW 0x0`	`BACK_END_POWER_7` `RW 0x0`	`BACK_END_POWER_6` `RW 0x0`	`BACK_END_POWER_5` `RW 0x0`	`BACK_END_POWER_4` `RW 0x0`	`BACK_END_POWER_3` `RW 0x0`	`BACK_END_POWER_2` `RW 0x0`	`BACK_END_POWER_1` `RW 0x0`	`BACK_END_POWER_0` `RW 0x0`
`UHS_REG_EXT` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`EXT_CLK_MUX_CTRL` `RW 0x0`		`CLK_DRV_PHASE_CTRL` `RW 0x0`							`CLK_SMPL_PHASE_CTRL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MMC_VOLT_REG_15` `RW 0x0`	`MMC_VOLT_REG_14` `RW 0x0`	`MMC_VOLT_REG_13` `RW 0x0`	`MMC_VOLT_REG_12` `RW 0x0`	`MMC_VOLT_REG_11` `RW 0x0`	`MMC_VOLT_REG_10` `RW 0x0`	`MMC_VOLT_REG_9` `RW 0x0`	`MMC_VOLT_REG_8` `RW 0x0`	`MMC_VOLT_REG_7` `RW 0x0`	`MMC_VOLT_REG_6` `RW 0x0`	`MMC_VOLT_REG_5` `RW 0x0`	`MMC_VOLT_REG_4` `RW 0x0`	`MMC_VOLT_REG_3` `RW 0x0`	`MMC_VOLT_REG_2` `RW 0x0`	`MMC_VOLT_REG_1` `RW 0x0`	`MMC_VOLT_REG_0` `RW 0x0`
`EMMC_DDR_REG` `0x10C` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`HS400_MODE` `RO 0x0`	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`HALF_START_BIT_0` `RW 0x0`
`ENABLE_SHIFT` `0x110` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`ENABLE_SHIFT_CARD0` `RW 0x0`
`DATA` `0x200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`