BMOD 

         
Name: Bus Mode Register
Size: 32 bits
Address Offset: 0x80
Read/Write access: read/write
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_0 0xFF808000 0xFF808080

Size: 32

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

PBL

RO 0x0

DE

RW 0x0

DSL

RW 0x0

FB

RW 0x0

SWR

RW 0x0

BMOD Fields

Bit Name Description Access Reset
10:8 PBL 
Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value
to FIFOTH register. This is an encode value as follows.
                                                 000  1 transfers
                                                 001  4 transfers
                                                 010  8 transfers
                                                 011  16 transfers
                                                 100  32 transfers
                                                 101  64 transfers
                                                 110  128 transfers
                                                 111  256 transfers
Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH.
PBL is a read-only value and is applicable only for Data Access; it does not apply to descriptor accesses.
Value Description
0x0 Burst of 1
0x1 Burst of 4
0x2 Burst of 8
0x3 Burst of 16
0x4 Burst of 32
0x5 Burst of 64
0x6 Burst of 128
0x7 Burst of 256
RO 0x0
7 DE 
IDMAC Enable. When set, the IDMAC is enabled.
DE is read/write.
Value Description
0x0 IDMAC is disabled
0x1 When set, the IDMAC is enabled
RW 0x0
6:2 DSL 
Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable only for dual buffer structure.
DSL is read/write.
 RW 0x0
1 FB 
Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set,the AHB will use only SINGLE, INCR4, INCR8 or
INCR16 during start of normal burst transfers.When reset,the AHB will use SINGLE and INCR burst transfer operations.
FB is read/write.
Value Description
0x0 SINGLE and INCR burst transfer
0x1 SINGLE, INCR4, INCR8, or INCR16 transfers
RW 0x0
0 SWR 
Software Reset.When set,the DMA Controller resets all its internal registers.
SWR is read/write. It is automatically cleared after 1 clock cycle.
Value Description
0x0 No change
0x1 DMA controller reset
RW 0x0