STATUS 

         
Name: Status Register
Size: 32 bits
Address Offset: 0x48
Read/write access: read
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_0 0xFF808000 0xFF808048

Size: 32

Offset: 0x48

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DMA_REQ

RO 0x0

DMA_ACK

RO 0x0

FIFO_COUNT

RO 0x0

RESPONSE_INDEX

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESPONSE_INDEX

RO 0x0

DATA_STATE_MC_BUSY

RO 0x0

DATA_BUSY

RO 0x0

DATA_3_STATUS

RO 0x1

COMMAND_FSM_STATES

RO 0x0

FIFO_FULL

RO 0x0

FIFO_EMPTY

RO 0x1

FIFO_TX_WATERMARK

RO 0x1

FIFO_RX_WATERMARK

RO 0x0

STATUS Fields

Bit Name Description Access Reset
31 DMA_REQ 
DMA request signal state; either dw_dma_req or ge_dma_req,
depending on DW-DMA or Generic-DMA selection.
Value Description
0x0 DMA request not asserted
0x1 DMA request asserted
RO 0x0
30 DMA_ACK 
DMA acknowledge signal state; either dw_dma_ack or
ge_dma_ack, depending on DW-DMA or Generic-DMA selection.
Value Description
0x0 DMA ack not asserted
0x1 DMA ack asserted
RO 0x0
29:17 FIFO_COUNT 
FIFO count Number of filled locations in FIFO
 RO 0x0
16:11 RESPONSE_INDEX 
Index of previous response, including any auto-stop sent by core
 RO 0x0
10 DATA_STATE_MC_BUSY 
Data transmit or receive state-machine is busy
Value Description
0x0 DMA state-machine not busy
0x1 DMA state-machine busy
RO 0x0
9 DATA_BUSY 
Inverted version of raw selected card_data[0]
                                                 0-card data not busy
                                                 1-card data busy
Value Description
0x0 Card data not busy
0x1 card data busy
RO 0x0
8 DATA_3_STATUS 
Raw selected card_data[3]; checks whether card is present
                                                 0-card not present
                                                 1-card present
Value Description
0x0 Card not present
0x1 card present
RO 0x1
7:4 COMMAND_FSM_STATES 
Command FSM states:
                                                 0  Idle
                                                 1  Send init sequence
                                                 2  Tx cmd start bit
                                                 3  Tx cmd tx bit
                                                 4  Tx cmd index + arg
                                                 5  Tx cmd crc7
                                                 6  Tx cmd end bit
                                                 7  Rx resp start bit
                                                 8  Rx resp IRQ response
                                                 9  Rx resp tx bit
                                                 10  Rx resp cmd idx
                                                 11  Rx resp data
                                                 12  Rx resp crc7
                                                 13  Rx resp end bit
                                                 14  Cmd path wait NCC
                                                 15  Wait; CMD-to-response turnaround
NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:
 * Bit 16  Wait for CCS
 * Bit 17  Send CCSD
 * Bit 18  Boot Mode
Due to this, while command FSM is in “Wait for CCS state” or “Send CCSD” or “Boot Mode”, the Status register indicates status as 0 for the bit field 7:4.
 RO 0x0
3 FIFO_FULL 
FIFO is full status
Value Description
0x0 FIFO is not full
0x1 FIFO is full
RO 0x0
2 FIFO_EMPTY 
FIFO is empty status
Value Description
0x0 FIFO is not empty
0x1 FIFO is empty
RO 0x1
1 FIFO_TX_WATERMARK 
FIFO reached Transmit watermark level; not qualified with data
transfer.
Value Description
0x0 Not reached TXWMARK level
0x1 Reached TXWMARK level
RO 0x1
0 FIFO_RX_WATERMARK 
FIFO reached Receive watermark level; not qualified with data
transfer.
Value Description
0x0 Not reached RXWMARK level
0x1 Reached RXWMARK level
RO 0x0