Control_Status Address Map

Registers in the Clock Manager module
Module Instance Base Address End Address
i_clk_mgr_clkmgr 0xFFD10000 0xFFD10023
Register Offset Width Access Reset Value Description
ctrl 0x0 32 RW 0x00000003 
Control Register
stat 0x4 32 RO 0x001C1C00 
Status Register
testioctrl 0x8 32 RW 0x00100808 
Test IO Control Register
intrgen 0xC 32 RW 0x00000000 
Global Interrupt Enable

Writing 0 will disable any functions from this IP to cause a hardware interrupt.
Interrupt pending status register can still be set but the hardware interrupt signal will remain de-asserted.

Writing 1 will enable the hardware interrupt from this IP.
intrmsk 0x10 32 RW 0x00000000 
Interrupt Mask

A 0 in the curresponding bitfield will mask that particular interrupt.
intrclr 0x14 32 WO 0x00000000 
Interrupt Clear.

Writing 1 to a particular bit will cause that interrupt to be cleared if it was set.
intrsts 0x18 32 RO 0x00000000 
Interrupt Pending Status after the interrupt masks.

Set by hardware and read by software.
Sticky behavior. Once set by hardware, the bit will remain set, till cleared by software by writing to intrclr register.
The status for a particular bit would be read as 0, if the curresponding mask bit is set.
intrstk 0x1C 32 RO 0x00000000 
Interrupt Pending Status without considering the interrupt masks.

Set by hardware and read by software.
Hardware can set the particular bit, even if the corresponding bit is masked by software by intrmsk register.
Sticky behavior. Once set by hardware, the bit will remain set, till cleared by software by writing to intrclr register.
intrraw 0x20 32 RO 0x00000000 
Realtime Status of the bits which could have caused interrupt.

Set and clear by hardware.
Realtime behavior. Bits follow the current hardware status.