stat 

         Provides status for Clock Manager including PLL lock and HW Managed Clock State Machine busy.
Module Instance Base Address Register Address
i_clk_mgr_clkmgr 0xFFD10000 0xFFD10004

Size: 32

Offset: 0x4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

bootclksrc

RO 0x0

bootmode

RO 0x0

Reserved

perf_trans

RO 0x0

perplllocked

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

main_trans

RO 0x0

mainplllocked

RO 0x0

Reserved

busy

RO 0x0

stat Fields

Bit Name Description Access Reset
25 bootclksrc 
If 1, the source of boot_clk is cb_intosc_hs_div2_clk.  . If 0, the boot_clk source is the external oscillator (EOSC1).

This is a read only status.
 RO 0x0
24 bootmode 
If 1, the clocks are currently in Boot Mode. If 0, the clocks are not in Boot Mode.

This is a read only status.  For SW to exit Boot Mode, SW must clear the RW bit CTRL.BOOTMODE.
 RO 0x0
17 perf_trans 
HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Peripheral PLL.
1—Completed
0—In transition
Value Description
0 State In Transition
1 State Transition Completed
RO 0x0
16 perplllocked 
PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers. 
The PPM threshold can only be updated while the HP PLL IP is in PD state.

If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is currently not locked.
RO 0x0
9 main_trans 
HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Main PLL.
1—Completed
0—In transition
Value Description
0 State In Transition
1 State Transition Completed
RO 0x0
8 mainplllocked 
PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers. 
The PPM threshold can only be updated while the HP PLL IP is in PD state.

If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not locked.
 RO 0x0
0 busy 
This read only bit indicates that the Hardware Managed clock's state machine is active.  If the state machine is active, then the clocks are in transition.   Software should poll this bit after changing the source of internal clocks when changing the state of CTRL.BOOTMODE, MAINPLLGRP.BYPASS.MPU or MAINPLLGRP.BYPASS.NOC register bits.   Immediately following writes to any of these registers, SW should wait 0.5 usecs and then poll this BUSY bit until it is IDLE before proceeding with any other register writes in the Clock Manager.

The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.
Value Description
0 Clocks stable
1 Clocks in transition
RO 0x0