testioctrl

         Contains fields setting the IO output select for Test Clock and Debug outputs.    

For debug purpose, clock manager send the PLL clocks and PLL lock status out to the dedicated IO and DFT fabric. Dedicated IO expects 4 signals from clock manager i.e. osc_clk, main pll c0/c1/c2/c3, peripheral pll c0/c1/c2/c3 and lock status.

testioctrl_debugclksel is used to select between main pll lock and peripheral pll lock status 
testioctrl_mainclksel is used to select between channel 0, channel 1,channel 2 and channel 3 of main PLL
testioctrl_peripclksel is used to select between channel 0, channel 1,channel 2 and channel 3 of peripheral PLL

Module Instance	Base Address	Register Address
`i_clk_mgr_clkmgr`	`0xFFD10000`	`0xFFD10008`

Size: 32

Offset: 0x8

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`debugclksel` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`periclksel` `RW 0x0`		`Reserved`						`mainclksel` `RW 0x0`

testioctrl Fields

Bit

Name

Description

Access

Reset

debugclksel

Selects the source of PLL_lock for debug purpose.

0 -main PLL lock
1- peri pLL lock

Value	Description
0	MAIN
1	PERIPH

RW

0x0

9:8

periclksel

Selects between Channel 0, Channel 1, Channel2 and Channel 3 of the peripheral PLL.

0 -> periph PLL C0
1 -> periph PLL C1
2 -> periph PLL C2
3 -> periph PLL C3

Value	Description
0	MPU_CHANNEL_C0
1	NOC_CHANNEL_C1
2	CHANNEL_C2
3	CHANNEL_C3

RW

0x0

1:0

mainclksel

Selects between Channel 0, Channel 1, Channel 2 and Channel 3 of the main PLL.

0 -> main PLL C0
1 -> main PLL C1
2 -> main PLL C2
3 -> main PLL C3

Value	Description
0	MPU_CHANNEL_C0
1	NOC_CHANNEL_C1
2	CHANNEL_C2
3	CHANNEL_C3

RW

0x0