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  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
  3. Altera® FPGA Intellectual Property
  4. Memory Interface and Controllers IP Cores
  5. DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP

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DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP

DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements in speed and power efficiency. LPDDR4 and LPDDR5 are optimized for low power consumption, making them ideal for embedded applications, with LPDDR5 offering even faster data rates and improved energy management. When integrated with Altera FPGAs these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud and edge.

agilex fpga hard memory controller

Hardening the Controller and PHY Offers Several Advantages which Include:

  • Shorter development cycles and faster time to market due to pre-closed timing
  • More FPGA fabric logic resources available for user application
  • Improved fmax, efficiency and latency
  • Low power solution

Utilize these advantages on Agilex™ 3, 5, and 7 devices, Stratix® 10 devices, and Arria® 10 FPGAs across various applications: industrial, wireless/wireline, broadcast, medical, retail, test measurement, and more.

Watch the Agilex™ 5 FPGA E-Series EMIF quick video ›

Watch the Agilex™ 5 FPGA D-Series EMIF quick video ›

  • Ordering Information
  • Documentation
  • Key Features
IP Included in Quartus® Prime Design Software Ordering Codes
DDR5 and DDR4 EMIF FPGA IP Yes No ordering code required
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Agilex™ 3 FPGA EMIF User Guide

Agilex™ 5 FPGA EMIF User Guide

Agilex™ 5 FPGA EMIF Design Example User Guide

Agilex™ 7 FPGA M-Series EMIF IP User Guide

Agilex™ 7 FPGA M-Series EMIF Design Example User Guide

Agilex™ 7 FPGA F-Series and I-Series EMIF IP User Guide

Agilex™ 7 FPGA F-Series and I-Series EMIF Design Example User Guide

Stratix® 10 FPGA EMIF User Guide

Stratix® 10 FPGA EMIF Design Example User Guide

EMIF Protocols & Features

Feature

Agilex™ 3 FPGAs

Agilex™ 5 FPGAs

Agilex™ 7 FPGA M-Series

Agilex™ 7 FPGA I- and F- Series

Stratix® 10 FPGA

DDR5

No

Yes

Yes

No

No

LPDDR5

No

Yes

Yes

No

No

DDR4

No

Yes

Yes

Yes

Yes

LPDDR4

Yes

Yes

No

No

No

QDRIV

No

No

No

Yes

Yes

Maximum Interface Width

X32 (LPDDR4)

X72 (DDR4)

X80 (DDR5)

X72 (DDR4)

X72 (DDR4)

Maximum Interface Rate

2133 Mbps

4667 Mbps (LPDDR5)

5600 Mbps (DDR5)

3200 Mbps

2666 Mbps

Maximum Ranks Supported

2

2

2

4

4

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Debug Features

EMIF Debug toolkit features include the below basic and advanced debug capabilities:

  • Viewing calibration margin, status, pin delay and VREF settings
  • Re-running calibration, traffic generator, and driver margining
  • Updating delay settings, and termination settings
  • Configurable Traffic Generator to send test traffic patterns

Agilex™ 5 FPGA In-Action External Memory Interfaces IP

Watch the demo on the High-Speed External Memory Interfaces that we offer on the Agilex 5 devices. 

Related Links

Device Support

  • Agilex™ 3 FPGAs ›
  • Agilex™ 5 FPGAs ›
  • Agilex™ 7 FPGAs ›
  • Stratix® 10 FPGAs ›
  • Arria® 10 FPGAs ›

Other

  • External Memory Interfaces IP Support Center ›
  • EMIF Spec Estimator ›
  • Intel® FPGA Technical Training Catalog ›

Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

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