Agilex™ 3 FPGA and SoC FPGA
Bringing high performance and power to cost-optimized and compact form factor FPGAs, which enables innovators to reach the next level of performance for their optimized designs.
Agilex™ 3 FPGA and SoC FPGA
Optimized for Cost-Effective and Space-Efficient Designs
Up to
1.9X
higher fabric performance1
Up to
38%
lower total power vs. competing FPGAs1
Up to
12.5Gbps
transceivers
Up to
1.9X
higher fabric performance1
Up to
38%
lower total power vs. competing FPGAs1
Up to
12.5Gbps
transceivers
Benefits
Upgraded Performance
Agilex 3 brings the high-performance Hyperflex™ FPGA architecture to power and cost-optimized applications. With 12.5 Gbps transceivers, 1.25 Gbps low-voltage differential signaling (LVDS), and 2.5G MIPI D-PHY, which improves system bandwidth, your data can get into and out of the FPGA, reducing data bottlenecks.
Higher Integration
AI-optimized DSPs with tensor blocks and hardened IP blocks deliver robust capabilities in a single chip while supporting dual Cortex ARM A55 cores. Utilizing innovative variable pitch BGA packaging technology enables these capabilities while maintaining low-cost manufacturing PCB design rules.
Security and Reliability
Secure your design with SHA-384 bitstream integrity, ECDSA 256/384 bitstream authentication, AES-256, PUF key, side-channel attack resistance, SPDM attestation, cryptographic services, and physical anti-tamper support.
Use Cases and Applications
Industrial
- AI in Smart Factory
- Smart Factory Automation
- Sensors/motors/connectivity, functional safety, and security
- I/O modules and IoT devices
- Tiny PLC and Edge AI
Surveillance, Retail, Consumer
- Smart city/retail, V2X
- Trucks, bus systems, trains and railways, EV charging
- Vision processing
Video Processing
- Connectivity and video processing
- Video over IP
- Consumer electronics (AR/VR, Drones, Gaming)
Medical
- Diagnostic imaging & video
- Patient monitoring
Key Features
Enhanced DSP with AI Tensor Block
Offers up to 2.8 peak INT8 TOPS with FPGA AI Suite support to enable push-button flow from industry standard frameworks to FPGA bitstream.
Transceivers
The GTS transceiver supports data rates up to 12.5 Gbps. It integrates hard IP support for PCIe 3.0 x4 and 10GbE, reducing design time and on-chip resources required.
SDM (Secure Device Manager)
Offering key security features such as secure boot, AES encryption, and FPGA configuration management, which runtime sensors and tamper detection, providing ensure authenticated FPGA configuration, support bitstream encryption, and manage enhanced protection against unauthorized access and data integrity threats.
Want to Learn More?
For documentation and product information, contact our sales team.
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.intel.com/PerformanceIndex. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary.